jian.hu 8ea2681953 clk: optimize clock regmap interface [1/1]
PD#SWPL-134344

Problem:
optimize clock regmap interface

Solution:
optimize clock regmap interface

Verify:
t5w/t3/t5m/t7c

Change-Id: I72b1e615e92c1667c3ed336ff42e5427074446c9
Signed-off-by: jian.hu <jian.hu@amlogic.com>
2024-01-20 09:04:35 +08:00
S
Description
No description provided
118 MiB
Languages
C 98.9%
Perl 0.4%
Makefile 0.4%
Shell 0.2%