Brian Zhu a141be7e05 di: fix first frame garbage for dct post with prelink [1/1] ...

PD#SWPL-141569

Problem:
dct post has clk gate timing issue with prelink mode

Solution:
1. disable clk gate mode for avg_flt module in dct post
2. add delay policy for dct post, not enable as default

Verify:
Verified on t5m

Change-Id: I805cddf07faa13c766f01485cdff0b60c7e0f65d
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>

2024-01-20 09:05:19 +08:00

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di: fix first frame garbage for dct post with prelink [1/1]

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