Chuan Liu ae4943530e clk: s7d: Fix known issue [1/1]
PD#SWPL-163050

Problem:
1 PLL driver adds rstn features
2 Add ACLKM clock
3 Adapts to pll_v4_ops

Solution:
Fixed

Verify:
s7d_bm209

Change-Id: Ide5199539d388d9ee415ecf65f3c162b2e4c881c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
2024-04-17 19:31:21 +08:00
2024-04-17 19:31:21 +08:00
2024-04-17 19:31:21 +08:00
2024-04-17 19:31:21 +08:00
2024-04-17 19:29:58 +08:00
S
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118 MiB
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Makefile 0.4%
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