jian.hu b07ac2b485 clk: optimize clock regmap interface [1/1]
PD#SWPL-134344

Problem:
optimize clock regmap interface

Solution:
optimize clock regmap interface

Verify:
t5w/t3/t5m/t7c

Change-Id: I72b1e615e92c1667c3ed336ff42e5427074446c9
Signed-off-by: jian.hu <jian.hu@amlogic.com>
2023-10-19 22:03:51 -07:00
2023-10-19 22:03:47 -07:00
2023-10-19 02:09:45 -07:00
S
Description
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118 MiB
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