qianqian.cai d60ddfb7bf deinterlace: dct need gate clock on [1/1]
PD#SWPL-184651

Problem:
the first time,video is not correct

Solution:
dct need gate clock on
bit21/16:dctnr.gclk ctrl
bit17:dcnt reg
bit19/18:dcntr core
bit21/20:dctr intf

Verify:
t5w

Change-Id: I26e6c8efde9e2a200ef92ad2bed280ad23cf0cef
Signed-off-by: qianqian.cai <qianqian.cai@amlogic.com>
2024-10-14 18:58:28 -07:00
2024-09-18 02:56:36 -07:00
S
Description
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118 MiB
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C 98.9%
Perl 0.4%
Makefile 0.4%
Shell 0.2%