Chuan Liu e76dceefdd clk: s6: Update the axi_clk register bits definition [1/1] ...

PD#SWPL-183185

Problem:
VLSI updated the axi_clk register bits definition in the document.

Solution:
Fixed

Verify:
s6_bl201

Change-Id: Ibb3e5f9c5a8d7cfce58932568f26ae3dc80e4c3c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-08-29 02:43:38 -07:00

..

drm

drm: optimize qms_brr_viclist function [1/1]

2024-08-15 04:00:48 -07:00

dt-bindings

clk: s6: Update the axi_clk register bits definition [1/1]

2024-08-29 02:43:38 -07:00

linux/amlogic

gdc: add uvswap for dewarp [1/1]

2024-08-28 05:45:30 -07:00

trace/events

drm: add rdma table for drm osd registers [1/1]

2024-07-17 23:57:23 -07:00

uapi/amlogic

amvecm: t6d bringup [1/1]

2024-08-22 14:27:51 +08:00