Chuan Liu e76dceefdd clk: s6: Update the axi_clk register bits definition [1/1] ...

PD#SWPL-183185

Problem:
VLSI updated the axi_clk register bits definition in the document.

Solution:
Fixed

Verify:
s6_bl201

Change-Id: Ibb3e5f9c5a8d7cfce58932568f26ae3dc80e4c3c
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>

2024-08-29 02:43:38 -07:00

android

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2024-08-27 05:57:23 -07:00

drivers

clk: s6: Update the axi_clk register bits definition [1/1]

2024-08-29 02:43:38 -07:00

include

clk: s6: Update the axi_clk register bits definition [1/1]

2024-08-29 02:43:38 -07:00

samples

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mk.sh

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modules_rename.txt

bazel: optimize and add some function [1/2]

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modules.bzl

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2024-08-28 16:05:06 -07:00

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