Xiangyu Cai eb643d76db vlock: change vlock phase when lock [1/1]
PD#SWPL-156059

Problem:
low latency more than 14ms

Solution:
change vlock phase

Verify:
t3x

Change-Id: I3b6676d76cd814669fd22bf03637d3d1a5c39273
Signed-off-by: Xiangyu Cai <xiangyu.cai@amlogic.com>
2024-03-06 01:19:30 -08:00
2024-02-25 22:55:19 -07:00
2024-01-22 12:48:43 +08:00
S
Description
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118 MiB
Languages
C 98.9%
Perl 0.4%
Makefile 0.4%
Shell 0.2%