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fb46eaa2f4d08e0edc6fd7d5758bd85ab41daf52
PD#SWPL-188251 Problem: HW test clock pll1 signal better than pll0 Solution: modify clock to pll1 Verify: bl208 Change-Id: I4900f969f2c6b9e9ec04e63dd105686936822de2 Signed-off-by: Yu Tu <yu.tu@amlogic.com>
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