Yu Tu fb46eaa2f4 pcie: modify clock to pll1 [1/1]
PD#SWPL-188251

Problem:
HW test clock pll1 signal better than pll0

Solution:
modify clock to pll1

Verify:
bl208

Change-Id: I4900f969f2c6b9e9ec04e63dd105686936822de2
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
2024-10-24 10:33:38 +08:00
2024-08-08 16:14:25 +08:00
2024-10-24 10:33:38 +08:00
2024-10-23 14:01:23 +08:00
2024-07-14 17:57:46 +08:00
S
Description
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118 MiB
Languages
C 98.9%
Perl 0.4%
Makefile 0.4%
Shell 0.2%