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arm64: dts: rockchip: rk3588-evb2 support

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Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: Iea0a39517411d2f6aa15a3ba6016ffef1fd9a191
This commit is contained in:
Wu Liangqing
2021-11-21 17:10:04 +08:00
committed by Tao Huang
parent ec9e7b000e
commit 01442ef09e
1 changed files with 133 additions and 1 deletions
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134
arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi
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@@ -88,6 +88,22 @@
io-channels = <&saradc 3>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;
};
vcc3v3_lcd_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd0_n";
@@ -121,6 +137,30 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>;
pinctrl-1 = <&uart9_gpios>;
BT,reset_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "ap6398s";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
WIFI,poweren_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&backlight {
@@ -184,6 +224,30 @@
pinctrl-0 = <&lcd_rst_gpio>;
};
&gmac1 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
tx_delay = <0x5c>;
/* rx_delay = <0x4f>; */
phy-handle = <&rgmii_phy>;
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
status = "okay";
@@ -260,10 +324,22 @@
status = "okay";
};
&mdio1 {
rgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
&mipi_dcphy1 {
status = "okay";
};
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
@@ -300,6 +376,12 @@
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touch {
touch_gpio: touch-gpio {
rockchip,pins =
@@ -313,17 +395,53 @@
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart9_gpios: uart9-gpios {
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_gpio: bt-gpio {
rockchip,pins =
<2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm3 {
pinctrl-0 = <&pwm3m1_pins>;
status = "okay";
pinctrl-0 = <&pwm3m1_pins>;
};
&sata0 {
status = "okay";
};
&sdio {
max-frequency = <150000000>;
no-sd;
no-mmc;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdiom0_pins>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
status = "okay";
};
@@ -352,7 +470,21 @@
rockchip,dp-lane-mux = <2 3>;
};
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
};
&vcc3v3_lcd_n {
gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vop {
assigned-clocks = <&cru DCLK_VOP0_SRC>,
<&cru DCLK_VOP1_SRC>,
<&cru DCLK_VOP2_SRC>,
<&cru DCLK_VOP3>;
assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>;
};