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media: rockchip: ispp: add the stream_v20
Change-Id: I0952cf0d226e07f7e760e74b2a248d89bf016472 Signed-off-by: Lian Xu <xu.lian@rock-chips.com>
This commit is contained in:
@@ -17,3 +17,15 @@ config VIDEO_ROCKCHIP_ISPP_FEC
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default n
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help
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Say y if enable fec independent.
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if VIDEO_ROCKCHIP_ISPP
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config VIDEO_ROCKCHIP_ISPP_VERSION_V10
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bool "ispp10 for rv1126 and rv1109"
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default y if CPU_RV1126
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config VIDEO_ROCKCHIP_ISPP_VERSION_V20
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bool "ispp20 for rk3588"
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default y if CPU_RK3588
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endif
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@@ -10,6 +10,14 @@ video_rkispp-objs += hw.o \
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stats.o \
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procfs.o
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video_rkispp-$(CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10) += \
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stream_v10.o \
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params_v10.o \
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video_rkispp-$(CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20) += \
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stream_v20.o \
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params_v20.o \
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ifdef CONFIG_VIDEO_ROCKCHIP_ISPP_FEC
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video_rkispp-objs += fec.o
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endif
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@@ -269,7 +269,7 @@ static void rkispp_free_pool(struct rkispp_hw_dev *hw)
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if (rkispp_debug)
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dev_info(hw->dev, "%s dbufs[%d]:0x%p\n",
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__func__, i, buf->dbufs);
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for (j = 0; j < GROUP_BUF_MAX; j++) {
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for (j = 0; j < hw->pool[0].group_buf_max; j++) {
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if (buf->mem_priv[j]) {
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g_ops->unmap_dmabuf(buf->mem_priv[j]);
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g_ops->detach_dmabuf(buf->mem_priv[j]);
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@@ -304,7 +304,7 @@ static int rkispp_init_pool(struct rkispp_hw_dev *hw, struct rkisp_ispp_buf *dbu
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if (rkispp_debug)
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dev_info(hw->dev, "%s dbufs[%d]:0x%p\n",
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__func__, i, dbufs);
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for (i = 0; i < GROUP_BUF_MAX; i++) {
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for (i = 0; i < hw->pool[0].group_buf_max; i++) {
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mem = g_ops->attach_dmabuf(hw->dev, dbufs->dbuf[i],
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dbufs->dbuf[i]->size, DMA_BIDIRECTIONAL);
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if (IS_ERR(mem)) {
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@@ -370,9 +370,10 @@ static void rkispp_queue_dmabuf(struct rkispp_hw_dev *hw, struct rkisp_ispp_buf
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hw->cur_dev_id = buf->index;
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ispp = hw->ispp[buf->index];
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vdev = &ispp->stream_vdev;
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val = (vdev->module_ens & ISPP_MODULE_TNR) ? ISPP_MODULE_TNR : ISPP_MODULE_NR;
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rkispp_params_cfg(&ispp->params_vdev, buf->frame_id);
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rkispp_module_work_event(ispp, buf, NULL, val, false);
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val = (vdev->module_ens & ISPP_MODULE_TNR) ? ISPP_MODULE_TNR :
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((vdev->module_ens & ISPP_MODULE_NR) ? ISPP_MODULE_NR : ISPP_MODULE_FEC);
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ispp->params_vdev.params_ops->rkispp_params_cfg(&ispp->params_vdev, buf->frame_id);
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vdev->stream_ops->rkispp_module_work_event(ispp, buf, NULL, val, false);
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}
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spin_unlock_irqrestore(&hw->buf_lock, lock_flags);
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@@ -17,11 +17,17 @@
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#define RKISPP_PLANE_Y 0
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#define RKISPP_PLANE_UV 1
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#define RKISPP_MAX_WIDTH 4416
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#define RKISPP_MAX_HEIGHT 3312
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#define RKISPP_MIN_WIDTH 66
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#define RKISPP_MIN_HEIGHT 258
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#define RKISPP_VIDEO_NAME_LEN 16
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#define RKISPP_MAX_WIDTH_V10 4416
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#define RKISPP_MAX_HEIGHT_V10 3312
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#define RKISPP_MIN_WIDTH_V10 66
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#define RKISPP_MIN_HEIGHT_V10 258
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#define RKISPP_MAX_WIDTH_V20 8188
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#define RKISPP_MAX_HEIGHT_V20 8188
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#define RKISPP_MIN_WIDTH_V20 128
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#define RKISPP_MIN_HEIGHT_V20 128
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#define RKISPP_VIDEO_NAME_LEN 16
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#define RKISPP_BUF_POOL_MAX RKISP_ISPP_BUF_MAX
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@@ -29,6 +35,7 @@ struct rkispp_device;
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enum rkispp_ver {
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ISPP_V10 = 0x00,
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ISPP_V20 = 0x01,
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};
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enum rkispp_event_cmd {
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@@ -43,6 +50,7 @@ struct rkispp_isp_buf_pool {
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void *mem_priv[GROUP_BUF_MAX];
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dma_addr_t dma[GROUP_BUF_MAX];
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void *vaddr[GROUP_BUF_MAX];
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u8 group_buf_max;
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};
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/* One structure per video node */
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@@ -144,17 +144,53 @@ static int rkispp_create_links(struct rkispp_device *ispp_dev)
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RKISPP_PAD_SINK_PARAMS, flags);
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if (ret < 0)
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return ret;
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ispp_dev->stream_vdev.module_ens = ISPP_MODULE_FEC;
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if (ispp_dev->ispp_ver == ISPP_V10) {
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/* stats links */
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flags = MEDIA_LNK_FL_ENABLED;
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source = &ispp_dev->ispp_sdev.sd.entity;
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sink = &ispp_dev->stats_vdev.vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE_STATS,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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/* stats links */
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flags = MEDIA_LNK_FL_ENABLED;
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source = &ispp_dev->ispp_sdev.sd.entity;
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sink = &ispp_dev->stats_vdev.vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE_STATS,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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/* output stream links */
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stream = &stream_vdev->stream[STREAM_S0];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_S1];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_S2];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_VIR];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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ispp_dev->stream_vdev.module_ens = ISPP_MODULE_NR | ISPP_MODULE_SHP;
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}
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/* output stream links */
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flags = rkispp_stream_sync ? 0 : MEDIA_LNK_FL_ENABLED;
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stream = &stream_vdev->stream[STREAM_MB];
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stream->linked = flags;
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@@ -165,40 +201,7 @@ static int rkispp_create_links(struct rkispp_device *ispp_dev)
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_S0];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_S1];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_S2];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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stream = &stream_vdev->stream[STREAM_VIR];
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stream->linked = flags;
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sink = &stream->vnode.vdev.entity;
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ret = media_create_pad_link(source, RKISPP_PAD_SOURCE,
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sink, 0, flags);
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if (ret < 0)
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return ret;
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/* default enable */
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ispp_dev->stream_vdev.module_ens = ISPP_MODULE_NR | ISPP_MODULE_SHP;
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return 0;
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}
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@@ -240,6 +243,8 @@ err_unreg_stream_vdevs:
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static const struct of_device_id rkispp_plat_of_match[] = {
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{
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.compatible = "rockchip,rv1126-rkispp-vir",
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}, {
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.compatible = "rockchip,rk3588-rkispp-vir",
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},
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{},
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};
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@@ -54,7 +54,7 @@ struct rkispp_device {
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u32 mis_val;
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wait_queue_head_t sync_onoff;
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bool stream_sync;
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u8 stream_max;
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void (*irq_hdl)(u32 mis, struct rkispp_device *dev);
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};
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#endif
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@@ -11,6 +11,7 @@
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#include <media/videobuf2-v4l2.h>
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#include <linux/pm_runtime.h>
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#include <linux/rkispp-config.h>
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#include <uapi/linux/rk-video-format.h>
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#include "hw.h"
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#include "ispp.h"
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@@ -270,7 +271,8 @@ static int fec_running(struct rkispp_fec_dev *fec,
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val = ALIGN(buf->width * out_mult, 16) >> 2;
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writel(val, base + RKISPP_FEC_WR_VIR_STRIDE);
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val = buf->height << 16 | buf->width;
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writel(val, base + RKISPP_FEC_PIC_SIZE);
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writel(val, base + RKISPP_FEC_DST_SIZE);
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writel(val, base + RKISPP_FEC_SRC_SIZE);
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writel(mesh_size, base + RKISPP_FEC_MESH_SIZE);
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val = SW_FEC_EN | density;
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writel(val, base + RKISPP_FEC_CORE_CTRL);
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@@ -293,7 +295,8 @@ static int fec_running(struct rkispp_fec_dev *fec,
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RKISPP_FEC_WR_Y_BASE_SHD, readl(base + RKISPP_FEC_WR_Y_BASE_SHD),
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RKISPP_FEC_WR_UV_BASE_SHD, readl(base + RKISPP_FEC_WR_UV_BASE_SHD),
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RKISPP_FEC_CORE_CTRL, readl(base + RKISPP_FEC_CORE_CTRL),
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RKISPP_FEC_PIC_SIZE, readl(base + RKISPP_FEC_PIC_SIZE),
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RKISPP_FEC_DST_SIZE, readl(base + RKISPP_FEC_DST_SIZE),
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RKISPP_FEC_SRC_SIZE, readl(base + RKISPP_FEC_SRC_SIZE),
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RKISPP_FEC_MESH_SIZE, readl(base + RKISPP_FEC_MESH_SIZE));
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if (!fec->hw->is_shutdown)
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writel(FEC_ST, base + RKISPP_CTRL_STRT);
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@@ -452,6 +455,7 @@ int rkispp_register_fec(struct rkispp_hw_dev *hw)
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fec->vfd = fec_videodev;
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vfd = &fec->vfd;
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vfd->device_caps = V4L2_CAP_STREAMING;
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vfd->lock = &fec->apilock;
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vfd->v4l2_dev = v4l2_dev;
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ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
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@@ -424,6 +424,7 @@ static long rkispp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
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rkispp_reg_withstream = arg;
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*rkispp_reg_withstream = rkispp_is_reg_withstream_global();
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break;
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#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10)
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case RKISPP_CMD_TRIGGER_YNRRUN:
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rkispp_sendbuf_to_nr(ispp_dev, (struct rkispp_tnr_inf *)arg);
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break;
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@@ -433,6 +434,7 @@ static long rkispp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
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case RKISPP_CMD_TRIGGER_MODE:
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rkispp_set_trigger_mode(ispp_dev, (struct rkispp_trigger_mode *)arg);
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break;
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#endif
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default:
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ret = -ENOIOCTLCMD;
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}
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@@ -15,596 +15,6 @@
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#define RKISP1_ISP_PARAMS_REQ_BUFS_MIN 2
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#define RKISP1_ISP_PARAMS_REQ_BUFS_MAX 8
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#define ISPP_PACK_4BIT(a, b, c, d, e, f, g, h) \
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(((a) & 0xf) << 0 | ((b) & 0xf) << 4 | \
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((c) & 0xf) << 8 | ((d) & 0xf) << 12 | \
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((e) & 0xf) << 16 | ((f) & 0xf) << 20 | \
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((g) & 0xf) << 24 | ((h) & 0xf) << 28)
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#define ISPP_PACK_4BYTE(a, b, c, d) \
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(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
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((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
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#define ISPP_PACK_2SHORT(a, b) \
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(((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
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#define ISPP_NOBIG_OVERFLOW_SIZE (2560 * 1440)
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static inline size_t get_input_size(struct rkispp_params_vdev *params_vdev)
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{
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struct rkispp_device *dev = params_vdev->dev;
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struct rkispp_subdev *isp_sdev = &dev->ispp_sdev;
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return isp_sdev->out_fmt.width * isp_sdev->out_fmt.height;
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}
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static void tnr_config(struct rkispp_params_vdev *params_vdev,
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struct rkispp_tnr_config *arg)
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{
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u32 i, val;
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val = arg->opty_en << 2 | arg->optc_en << 3 |
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arg->gain_en << 4;
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rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CORE_CTRL,
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SW_TNR_OPTY_EN | SW_TNR_OPTC_EN |
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SW_TNR_GLB_GAIN_EN, val);
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val = ISPP_PACK_4BYTE(arg->pk0_y, arg->pk1_y,
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arg->pk0_c, arg->pk1_c);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_PK0, val);
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val = ISPP_PACK_2SHORT(arg->glb_gain_cur, arg->glb_gain_nxt);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GLB_GAIN, val);
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val = ISPP_PACK_2SHORT(arg->glb_gain_cur_div, arg->glb_gain_cur_sqrt);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GLB_GAIN_DIV, val);
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for (i = 0; i < TNR_SIGMA_CURVE_SIZE - 1; i += 2)
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_Y01 + i * 2,
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ISPP_PACK_2SHORT(arg->sigma_y[i], arg->sigma_y[i + 1]));
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_Y10, arg->sigma_y[16]);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_X18,
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ISPP_PACK_4BIT(arg->sigma_x[0], arg->sigma_x[1],
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arg->sigma_x[2], arg->sigma_x[3],
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arg->sigma_x[4], arg->sigma_x[5],
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arg->sigma_x[6], arg->sigma_x[7]));
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_X910,
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ISPP_PACK_4BIT(arg->sigma_x[8], arg->sigma_x[9],
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arg->sigma_x[10], arg->sigma_x[11],
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arg->sigma_x[12], arg->sigma_x[13],
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arg->sigma_x[14], arg->sigma_x[15]));
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for (i = 0; i < TNR_LUMA_CURVE_SIZE; i += 2) {
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val = ISPP_PACK_2SHORT(arg->luma_curve[i], arg->luma_curve[i + 1]);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_LUMACURVE_Y01 + i * 2, val);
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}
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val = ISPP_PACK_2SHORT(arg->txt_th0_y, arg->txt_th1_y);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_Y, val);
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val = ISPP_PACK_2SHORT(arg->txt_th0_c, arg->txt_th1_c);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_C, val);
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val = ISPP_PACK_2SHORT(arg->txt_thy_dlt, arg->txt_thc_dlt);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_DLT, val);
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val = ISPP_PACK_4BYTE(arg->gfcoef_y0[0], arg->gfcoef_y0[1],
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arg->gfcoef_y0[2], arg->gfcoef_y0[3]);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y0_0, val);
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val = ISPP_PACK_4BYTE(arg->gfcoef_y0[4], arg->gfcoef_y0[5], 0, 0);
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rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y0_1, val);
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val = ISPP_PACK_4BYTE(arg->gfcoef_y1[0], arg->gfcoef_y1[1],
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arg->gfcoef_y1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y2[0], arg->gfcoef_y2[1],
|
||||
arg->gfcoef_y2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y3[0], arg->gfcoef_y3[1],
|
||||
arg->gfcoef_y3[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y3, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg0[0], arg->gfcoef_yg0[1],
|
||||
arg->gfcoef_yg0[2], arg->gfcoef_yg0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg0[4], arg->gfcoef_yg0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg1[0], arg->gfcoef_yg1[1],
|
||||
arg->gfcoef_yg1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg2[0], arg->gfcoef_yg2[1],
|
||||
arg->gfcoef_yg2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg3[0], arg->gfcoef_yg3[1],
|
||||
arg->gfcoef_yg3[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG3, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl0[0], arg->gfcoef_yl0[1],
|
||||
arg->gfcoef_yl0[2], arg->gfcoef_yl0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl0[4], arg->gfcoef_yl0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl1[0], arg->gfcoef_yl1[1],
|
||||
arg->gfcoef_yl1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl2[0], arg->gfcoef_yl2[1],
|
||||
arg->gfcoef_yl2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL2, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg0[0], arg->gfcoef_cg0[1],
|
||||
arg->gfcoef_cg0[2], arg->gfcoef_cg0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg0[4], arg->gfcoef_cg0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg1[0], arg->gfcoef_cg1[1],
|
||||
arg->gfcoef_cg1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg2[0], arg->gfcoef_cg2[1],
|
||||
arg->gfcoef_cg2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG2, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl0[0], arg->gfcoef_cl0[1],
|
||||
arg->gfcoef_cl0[2], arg->gfcoef_cl0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl0[4], arg->gfcoef_cl0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl1[0], arg->gfcoef_cl1[1],
|
||||
arg->gfcoef_cl1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL1, val);
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yg[0], arg->scale_yg[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YG01, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yg[2], arg->scale_yg[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YG23, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yl[0], arg->scale_yl[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YL01, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YL2, arg->scale_yl[2]);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[0], arg->scale_y2cg[0]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG0, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[1], arg->scale_y2cg[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG1, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[2], arg->scale_y2cg[2]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG2, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cl[0], arg->scale_y2cl[0]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL0, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cl[1], arg->scale_y2cl[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL1, val);
|
||||
val = arg->scale_y2cl[2] << 16;
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->weight_y[0], arg->weight_y[1],
|
||||
arg->weight_y[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_WEIGHT, val);
|
||||
}
|
||||
|
||||
static bool is_tnr_enable(struct rkispp_params_vdev *params_vdev)
|
||||
{
|
||||
u32 cur_en;
|
||||
|
||||
cur_en = rkispp_read(params_vdev->dev, RKISPP_TNR_CORE_CTRL);
|
||||
cur_en &= SW_TNR_EN;
|
||||
|
||||
return (!!cur_en);
|
||||
}
|
||||
|
||||
static void tnr_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
if (en && !is_tnr_enable(params_vdev))
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CTRL, 0, SW_TNR_1ST_FRM);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CORE_CTRL, SW_TNR_EN, en);
|
||||
}
|
||||
|
||||
static void nr_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_nr_config *arg)
|
||||
{
|
||||
u32 i, val;
|
||||
u8 big_en, nobig_en, sd32_self_en = 0;
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_1SIGMA,
|
||||
arg->uvnr_gain_1sigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_OFFSET,
|
||||
arg->uvnr_gain_offset);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_gain_uvgain[0],
|
||||
arg->uvnr_gain_uvgain[1], arg->uvnr_gain_t2gen,
|
||||
arg->uvnr_gain_iso);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_GBLGAIN, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1GEN_M3ALPHA,
|
||||
arg->uvnr_t1gen_m3alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_MODE,
|
||||
arg->uvnr_t1flt_mode);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_MSIGMA,
|
||||
arg->uvnr_t1flt_msigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_WTP,
|
||||
arg->uvnr_t1flt_wtp);
|
||||
for (i = 0; i < NR_UVNR_T1FLT_WTQ_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t1flt_wtq[i],
|
||||
arg->uvnr_t1flt_wtq[i + 1], arg->uvnr_t1flt_wtq[i + 2],
|
||||
arg->uvnr_t1flt_wtq[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_WTQ0 + i, val);
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_M3ALPHA,
|
||||
arg->uvnr_t2gen_m3alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_MSIGMA,
|
||||
arg->uvnr_t2gen_msigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_WTP,
|
||||
arg->uvnr_t2gen_wtp);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t2gen_wtq[0],
|
||||
arg->uvnr_t2gen_wtq[1], arg->uvnr_t2gen_wtq[2],
|
||||
arg->uvnr_t2gen_wtq[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_WTQ, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2FLT_MSIGMA,
|
||||
arg->uvnr_t2flt_msigma);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t2flt_wtp,
|
||||
arg->uvnr_t2flt_wt[0], arg->uvnr_t2flt_wt[1],
|
||||
arg->uvnr_t2flt_wt[2]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2FLT_WT, val);
|
||||
|
||||
val = ISPP_PACK_4BIT(arg->ynr_sgm_dx[0], arg->ynr_sgm_dx[1],
|
||||
arg->ynr_sgm_dx[2], arg->ynr_sgm_dx[3],
|
||||
arg->ynr_sgm_dx[4], arg->ynr_sgm_dx[5],
|
||||
arg->ynr_sgm_dx[6], arg->ynr_sgm_dx[7]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_SGM_DX_1_8, val);
|
||||
val = ISPP_PACK_4BIT(arg->ynr_sgm_dx[8], arg->ynr_sgm_dx[9],
|
||||
arg->ynr_sgm_dx[10], arg->ynr_sgm_dx[11],
|
||||
arg->ynr_sgm_dx[12], arg->ynr_sgm_dx[13],
|
||||
arg->ynr_sgm_dx[14], arg->ynr_sgm_dx[15]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_SGM_DX_9_16, val);
|
||||
|
||||
for (i = 0; i < NR_YNR_SGM_Y_SIZE - 1; i += 2) {
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LSGM_Y_0_1 + i * 2,
|
||||
ISPP_PACK_2SHORT(arg->ynr_lsgm_y[i], arg->ynr_lsgm_y[i + 1]));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSGM_Y_0_1 + i * 2,
|
||||
ISPP_PACK_2SHORT(arg->ynr_hsgm_y[i], arg->ynr_hsgm_y[i + 1]));
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LSGM_Y_16, arg->ynr_lsgm_y[16]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSGM_Y_16, arg->ynr_hsgm_y[16]);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lci[0], arg->ynr_lci[1],
|
||||
arg->ynr_lci[2], arg->ynr_lci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lgain_min[0], arg->ynr_lgain_min[1],
|
||||
arg->ynr_lgain_min[2], arg->ynr_lgain_min[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LGAIN_DIRE_MIN, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_IGAIN_DIRE_MAX, arg->ynr_lgain_max);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lmerge_bound, arg->ynr_lmerge_ratio, 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LMERGE, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lweit_flt[0], arg->ynr_lweit_flt[1],
|
||||
arg->ynr_lweit_flt[2], arg->ynr_lweit_flt[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LWEIT_FLT, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hlci[0], arg->ynr_hlci[1],
|
||||
arg->ynr_hlci[2], arg->ynr_hlci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HLCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lhci[0], arg->ynr_lhci[1],
|
||||
arg->ynr_lhci[2], arg->ynr_lhci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LHCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hhci[0], arg->ynr_hhci[1],
|
||||
arg->ynr_hhci[2], arg->ynr_hhci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HHCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hgain_sgm[0], arg->ynr_hgain_sgm[1],
|
||||
arg->ynr_hgain_sgm[2], arg->ynr_hgain_sgm[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HGAIN_SGM, val);
|
||||
|
||||
for (i = 0; i < NR_YNR_HWEIT_D_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hweit_d[i], arg->ynr_hweit_d[i + 1],
|
||||
arg->ynr_hweit_d[i + 2], arg->ynr_hweit_d[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_D0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < NR_YNR_HGRAD_Y_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hgrad_y[i], arg->ynr_hgrad_y[i + 1],
|
||||
arg->ynr_hgrad_y[i + 2], arg->ynr_hgrad_y[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HGRAD_Y0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hweit[0], arg->ynr_hweit[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_1_2, val);
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hweit[2], arg->ynr_hweit[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_3_4, val);
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HMAX_ADJUST, arg->ynr_hmax_adjust);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTRENGTH, arg->ynr_hstrength);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lweit_cmp[0], arg->ynr_lweit_cmp[1], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LWEIT_CMP, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LMAXGAIN_LV4, arg->ynr_lmaxgain_lv4);
|
||||
|
||||
for (i = 0; i < NR_YNR_HSTV_Y_SIZE - 1; i += 2) {
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hstv_y[i], arg->ynr_hstv_y[i + 1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTV_Y_0_1 + i * 2, val);
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTV_Y_16, arg->ynr_hstv_y[16]);
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_st_scale[0], arg->ynr_st_scale[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_ST_SCALE_LV1_LV2, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_ST_SCALE_LV3, arg->ynr_st_scale[2]);
|
||||
|
||||
big_en = arg->uvnr_big_en & 0x01;
|
||||
nobig_en = arg->uvnr_nobig_en & 0x01;
|
||||
if (get_input_size(params_vdev) > ISPP_NOBIG_OVERFLOW_SIZE) {
|
||||
big_en = 1;
|
||||
nobig_en = 0;
|
||||
}
|
||||
|
||||
if (params_vdev->dev->hw_dev->dev_num == 1)
|
||||
sd32_self_en = arg->uvnr_sd32_self_en;
|
||||
val = arg->uvnr_step1_en << 1 | arg->uvnr_step2_en << 2 |
|
||||
arg->nr_gain_en << 3 | sd32_self_en << 4 |
|
||||
nobig_en << 5 | big_en << 6;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_NR_UVNR_CTRL_PARA,
|
||||
SW_UVNR_STEP1_ON | SW_UVNR_STEP2_ON |
|
||||
SW_NR_GAIN_BYPASS | SW_UVNR_NOBIG_EN |
|
||||
SW_UVNR_BIG_EN, val);
|
||||
}
|
||||
|
||||
static void nr_enable(struct rkispp_params_vdev *params_vdev, bool en,
|
||||
struct rkispp_nr_config *arg)
|
||||
{
|
||||
u8 big_en, nobig_en;
|
||||
u32 val;
|
||||
|
||||
big_en = arg->uvnr_big_en & 0x01;
|
||||
nobig_en = arg->uvnr_nobig_en & 0x01;
|
||||
if (get_input_size(params_vdev) > ISPP_NOBIG_OVERFLOW_SIZE) {
|
||||
big_en = 1;
|
||||
nobig_en = 0;
|
||||
}
|
||||
|
||||
val = arg->uvnr_step1_en << 1 | arg->uvnr_step2_en << 2 |
|
||||
arg->nr_gain_en << 3 | nobig_en << 5 | big_en << 6;
|
||||
|
||||
if (en)
|
||||
val |= SW_NR_EN;
|
||||
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_NR_UVNR_CTRL_PARA,
|
||||
SW_UVNR_STEP1_ON | SW_UVNR_STEP2_ON |
|
||||
SW_NR_GAIN_BYPASS | SW_UVNR_NOBIG_EN |
|
||||
SW_UVNR_BIG_EN | SW_NR_EN, val);
|
||||
}
|
||||
|
||||
static void shp_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_sharp_config *arg)
|
||||
{
|
||||
u32 i, val;
|
||||
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CTRL,
|
||||
SW_SHP_WR_ROT_MODE(3),
|
||||
SW_SHP_WR_ROT_MODE(arg->rotation));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_SC_DOWN,
|
||||
(arg->scl_down_v & 0x1) << 1 | (arg->scl_down_h & 0x1));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_TILE_IDX,
|
||||
(arg->tile_ycnt & 0x1F) << 8 | (arg->tile_xcnt & 0xFF));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_FACTOR, arg->hbf_ratio |
|
||||
arg->ehf_th << 16 | arg->pbf_ratio << 24);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_TH, arg->edge_thed |
|
||||
arg->dir_min << 8 | arg->smoth_th4 << 16);
|
||||
val = ISPP_PACK_2SHORT(arg->l_alpha, arg->g_alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_ALPHA, val);
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_k[0], arg->pbf_k[1], arg->pbf_k[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_PBF_KERNEL, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mrf_k[0], arg->mrf_k[1], arg->mrf_k[2], arg->mrf_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MRF_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mrf_k[4], arg->mrf_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MRF_KERNEL1, val);
|
||||
|
||||
for (i = 0; i < SHP_MBF_KERNEL_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->mbf_k[i], arg->mbf_k[i + 1],
|
||||
arg->mbf_k[i + 2], arg->mbf_k[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MBF_KERNEL0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->hrf_k[0], arg->hrf_k[1], arg->hrf_k[2], arg->hrf_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HRF_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hrf_k[4], arg->hrf_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HRF_KERNEL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hbf_k[0], arg->hbf_k[1], arg->hbf_k[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_KERNEL, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->eg_coef[0], arg->eg_coef[1], arg->eg_coef[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_COEF, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_smoth[0], arg->eg_smoth[1], arg->eg_smoth[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_SMOTH, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_gaus[0], arg->eg_gaus[1], arg->eg_gaus[2], arg->eg_gaus[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_GAUS0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_gaus[4], arg->eg_gaus[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_GAUS1, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->dog_k[0], arg->dog_k[1], arg->dog_k[2], arg->dog_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DOG_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->dog_k[4], arg->dog_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DOG_KERNEL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_point[0], arg->lum_point[1],
|
||||
arg->lum_point[2], arg->lum_point[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_POINT0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_point[4], arg->lum_point[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_POINT1, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_shf_bits, arg->mbf_shf_bits, arg->hbf_shf_bits, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_SHF_BITS, val);
|
||||
|
||||
for (i = 0; i < SHP_SIGMA_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_sigma[i], arg->pbf_sigma[i + 1],
|
||||
arg->pbf_sigma[i + 2], arg->pbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_PBF_SIGMA_INV0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mbf_sigma[i], arg->mbf_sigma[i + 1],
|
||||
arg->mbf_sigma[i + 2], arg->mbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MBF_SIGMA_INV0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hbf_sigma[i], arg->hbf_sigma[i + 1],
|
||||
arg->hbf_sigma[i + 2], arg->hbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_SIGMA_INV0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_LUM_CLP_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->lum_clp_m[i], arg->lum_clp_m[i + 1],
|
||||
arg->lum_clp_m[i + 2], arg->lum_clp_m[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_CLP_M0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_clp_h[i], arg->lum_clp_h[i + 1],
|
||||
arg->lum_clp_h[i + 2], arg->lum_clp_h[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_CLP_H0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_LUM_MIN_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->lum_min_m[i], arg->lum_min_m[i + 1],
|
||||
arg->lum_min_m[i + 2], arg->lum_min_m[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_MIN_M0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_EDGE_LUM_THED_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->edge_lum_thed[i], arg->edge_lum_thed[i + 1],
|
||||
arg->edge_lum_thed[i + 2], arg->edge_lum_thed[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_LUM_THED0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_CLAMP_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->clamp_pos[i], arg->clamp_pos[i + 1],
|
||||
arg->clamp_pos[i + 2], arg->clamp_pos[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_CLAMP_POS_DOG0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->clamp_neg[i], arg->clamp_neg[i + 1],
|
||||
arg->clamp_neg[i + 2], arg->clamp_neg[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_CLAMP_NEG_DOG0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_DETAIL_ALPHA_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->detail_alpha[i], arg->detail_alpha[i + 1],
|
||||
arg->detail_alpha[i + 2], arg->detail_alpha[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DETAIL_ALPHA_DOG0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->rfl_ratio, arg->rfh_ratio);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_RF_RATIO, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->m_ratio, arg->h_ratio, 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_GRAD_RATIO, val);
|
||||
|
||||
val = arg->alpha_adp_en << 1 | arg->yin_flt_en << 3 |
|
||||
arg->edge_avg_en << 4;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CORE_CTRL,
|
||||
SW_SHP_ALPHA_ADP_EN | SW_SHP_YIN_FLT_EN |
|
||||
SW_SHP_EDGE_AVG_EN, val);
|
||||
}
|
||||
|
||||
static void shp_enable(struct rkispp_params_vdev *params_vdev, bool en,
|
||||
struct rkispp_sharp_config *arg)
|
||||
{
|
||||
u32 ens = params_vdev->dev->stream_vdev.module_ens;
|
||||
u32 val;
|
||||
|
||||
if (en && !(ens & ISPP_MODULE_FEC)) {
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL0_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL1_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL2_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
} else {
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL0_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL1_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL2_CTRL, SW_SCL_FIRST_MODE);
|
||||
}
|
||||
|
||||
val = arg->alpha_adp_en << 1 | arg->yin_flt_en << 3 |
|
||||
arg->edge_avg_en << 4;
|
||||
if (en)
|
||||
val |= SW_SHP_EN;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CORE_CTRL,
|
||||
SW_SHP_ALPHA_ADP_EN | SW_SHP_YIN_FLT_EN |
|
||||
SW_SHP_EDGE_AVG_EN | SW_SHP_EN, val);
|
||||
}
|
||||
|
||||
static void fec_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_fec_config *arg)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
struct rkispp_fec_head *fec_data;
|
||||
u32 width, height, mesh_size;
|
||||
dma_addr_t dma_addr;
|
||||
u32 val, i, buf_idx;
|
||||
|
||||
width = dev->ispp_sdev.out_fmt.width;
|
||||
height = dev->ispp_sdev.out_fmt.height;
|
||||
mesh_size = cal_fec_mesh(width, height, 0);
|
||||
if (arg->mesh_size > mesh_size) {
|
||||
v4l2_err(&dev->v4l2_dev,
|
||||
"Input mesh size too large. mesh size 0x%x, 0x%x\n",
|
||||
arg->mesh_size, mesh_size);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (arg->buf_fd == params_vdev->buf_fec[i].dma_fd)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_MESH_BUF_NUM) {
|
||||
dev_err(dev->dev, "cannot find fec buf fd(%d)\n", arg->buf_fd);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!params_vdev->buf_fec[i].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_INIT;
|
||||
|
||||
buf_idx = i;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_CHIPINUSE;
|
||||
params_vdev->buf_fec_idx = buf_idx;
|
||||
|
||||
rkispp_prepare_buffer(dev, ¶ms_vdev->buf_fec[buf_idx]);
|
||||
|
||||
dma_addr = params_vdev->buf_fec[buf_idx].dma_addr;
|
||||
val = dma_addr + fec_data->meshxf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshyf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshxi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XINT_BASE, val);
|
||||
val = dma_addr + fec_data->meshyi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YINT_BASE, val);
|
||||
|
||||
val = 0;
|
||||
if (arg->mesh_density)
|
||||
val = SW_MESH_DENSITY;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_MESH_DENSITY, val);
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_SIZE, arg->mesh_size);
|
||||
|
||||
val = (arg->crop_height & 0x1FFFF) << 14 |
|
||||
(arg->crop_width & 0x1FFFF) << 1 | (arg->crop_en & 0x01);
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_CROP, val);
|
||||
}
|
||||
|
||||
static void fec_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
u32 buf_idx;
|
||||
|
||||
if (en) {
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
if (!params_vdev->buf_fec[buf_idx].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL0_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL1_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL2_CTRL, SW_SCL_FIRST_MODE);
|
||||
}
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_FEC_EN, en);
|
||||
}
|
||||
|
||||
static void orb_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_orb_config *arg)
|
||||
{
|
||||
rkispp_write(params_vdev->dev, RKISPP_ORB_LIMIT_VALUE, arg->limit_value & 0xFF);
|
||||
rkispp_write(params_vdev->dev, RKISPP_ORB_MAX_FEATURE, arg->max_feature & 0x1FFFFF);
|
||||
}
|
||||
|
||||
static void orb_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_ORB_CORE_CTRL, SW_ORB_EN, en);
|
||||
}
|
||||
|
||||
static int rkispp_params_enum_fmt_meta_out(struct file *file, void *priv,
|
||||
struct v4l2_fmtdesc *f)
|
||||
{
|
||||
@@ -770,13 +180,18 @@ static int rkispp_params_vb2_queue_setup(struct vb2_queue *vq,
|
||||
struct device *alloc_ctxs[])
|
||||
{
|
||||
struct rkispp_params_vdev *params_vdev = vq->drv_priv;
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
|
||||
*num_buffers = clamp_t(u32, *num_buffers,
|
||||
RKISP1_ISP_PARAMS_REQ_BUFS_MIN,
|
||||
RKISP1_ISP_PARAMS_REQ_BUFS_MAX);
|
||||
|
||||
*num_planes = 1;
|
||||
sizes[0] = sizeof(struct rkispp_params_cfg);
|
||||
if (dev->ispp_ver == ISPP_V10)
|
||||
sizes[0] = sizeof(struct rkispp_params_cfg);
|
||||
else if (dev->ispp_ver == ISPP_V20)
|
||||
sizes[0] = sizeof(struct fec_params_cfg);
|
||||
|
||||
INIT_LIST_HEAD(¶ms_vdev->params);
|
||||
params_vdev->first_params = true;
|
||||
|
||||
@@ -785,33 +200,10 @@ static int rkispp_params_vb2_queue_setup(struct vb2_queue *vq,
|
||||
|
||||
static void rkispp_params_vb2_buf_queue(struct vb2_buffer *vb)
|
||||
{
|
||||
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
|
||||
struct rkispp_buffer *params_buf = to_rkispp_buffer(vbuf);
|
||||
struct vb2_queue *vq = vb->vb2_queue;
|
||||
struct rkispp_params_vdev *params_vdev = vq->drv_priv;
|
||||
struct rkispp_stream_vdev *stream_vdev = ¶ms_vdev->dev->stream_vdev;
|
||||
struct rkispp_params_cfg *new_params;
|
||||
unsigned long flags;
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)vb2_plane_vaddr(vb, 0);
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
if (params_vdev->first_params) {
|
||||
params_vdev->first_params = false;
|
||||
if (new_params->module_init_ens) {
|
||||
if (params_vdev->dev->hw_dev->is_fec_ext)
|
||||
new_params->module_init_ens &= ~ISPP_MODULE_FEC_ST;
|
||||
stream_vdev->module_ens = new_params->module_init_ens;
|
||||
|
||||
}
|
||||
wake_up(¶ms_vdev->dev->sync_onoff);
|
||||
}
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
|
||||
new_params->module_init_ens = stream_vdev->module_ens;
|
||||
params_buf->vaddr[0] = new_params;
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
list_add_tail(¶ms_buf->queue, ¶ms_vdev->params);
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
params_vdev->params_ops->rkispp_params_vb2_buf_queue(vb);
|
||||
}
|
||||
|
||||
static void rkispp_params_vb2_stop_streaming(struct vb2_queue *vq)
|
||||
@@ -945,114 +337,6 @@ rkispp_params_init_vb2_queue(struct vb2_queue *q,
|
||||
return vb2_queue_init(q);
|
||||
}
|
||||
|
||||
static void fec_data_abandon(struct rkispp_params_vdev *vdev,
|
||||
struct rkispp_params_cfg *params)
|
||||
{
|
||||
struct rkispp_fec_head *data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (params->fec_cfg.buf_fd == vdev->buf_fec[i].dma_fd) {
|
||||
data = (struct rkispp_fec_head *)vdev->buf_fec[i].vaddr;
|
||||
if (data)
|
||||
data->stat = FEC_BUF_INIT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rkispp_params_cfg(struct rkispp_params_vdev *params_vdev, u32 frame_id)
|
||||
{
|
||||
struct rkispp_params_cfg *new_params = NULL;
|
||||
u32 module_en_update, module_cfg_update, module_ens;
|
||||
|
||||
spin_lock(¶ms_vdev->config_lock);
|
||||
if (!params_vdev->streamon) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
/* get buffer by frame_id */
|
||||
while (!list_empty(¶ms_vdev->params) && !params_vdev->cur_buf) {
|
||||
params_vdev->cur_buf = list_first_entry(¶ms_vdev->params,
|
||||
struct rkispp_buffer, queue);
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
if (new_params->frame_id < frame_id) {
|
||||
if (new_params->module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_data_abandon(params_vdev, new_params);
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
continue;
|
||||
} else if (new_params->frame_id == frame_id) {
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
} else {
|
||||
params_vdev->cur_buf = NULL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!params_vdev->cur_buf) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
|
||||
module_en_update = new_params->module_en_update;
|
||||
module_cfg_update = new_params->module_cfg_update;
|
||||
module_ens = new_params->module_ens;
|
||||
if (params_vdev->dev->hw_dev->is_fec_ext) {
|
||||
module_en_update &= ~ISPP_MODULE_FEC;
|
||||
module_cfg_update &= ~ISPP_MODULE_FEC;
|
||||
module_ens &= ~ISPP_MODULE_FEC;
|
||||
}
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_TNR)
|
||||
tnr_config(params_vdev,
|
||||
&new_params->tnr_cfg);
|
||||
if (module_en_update & ISPP_MODULE_TNR)
|
||||
tnr_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_TNR));
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_NR)
|
||||
nr_config(params_vdev,
|
||||
&new_params->nr_cfg);
|
||||
if (module_en_update & ISPP_MODULE_NR)
|
||||
nr_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_NR),
|
||||
&new_params->nr_cfg);
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_SHP)
|
||||
shp_config(params_vdev,
|
||||
&new_params->shp_cfg);
|
||||
if (module_en_update & ISPP_MODULE_SHP)
|
||||
shp_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_SHP),
|
||||
&new_params->shp_cfg);
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_config(params_vdev,
|
||||
&new_params->fec_cfg);
|
||||
if (module_en_update & ISPP_MODULE_FEC)
|
||||
fec_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_FEC));
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_ORB)
|
||||
orb_config(params_vdev,
|
||||
&new_params->orb_cfg);
|
||||
if (module_en_update & ISPP_MODULE_ORB)
|
||||
orb_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_ORB));
|
||||
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf,
|
||||
VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
}
|
||||
|
||||
void rkispp_params_get_fecbuf_inf(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_fecbuf_info *fecbuf)
|
||||
{
|
||||
@@ -1086,7 +370,10 @@ int rkispp_register_params_vdev(struct rkispp_device *dev)
|
||||
|
||||
params_vdev->cur_params->module_cfg_update = 0;
|
||||
params_vdev->cur_params->module_en_update = 0;
|
||||
|
||||
if (dev->ispp_ver == ISPP_V10)
|
||||
rkispp_params_init_ops_v10(params_vdev);
|
||||
if (dev->ispp_ver == ISPP_V20)
|
||||
rkispp_params_init_ops_v20(params_vdev);
|
||||
spin_lock_init(¶ms_vdev->config_lock);
|
||||
strlcpy(vdev->name, "rkispp_input_params", sizeof(vdev->name));
|
||||
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#ifndef _RKISPP_PARAMS_H
|
||||
#define _RKISPP_PARAMS_H
|
||||
|
||||
#include <linux/fec-config.h>
|
||||
#include <linux/rkispp-config.h>
|
||||
#include "common.h"
|
||||
|
||||
@@ -14,13 +15,34 @@
|
||||
* cur_params: current buf of parameters
|
||||
* first_params: the first params should take effect immediately
|
||||
*/
|
||||
#define ISPP_PACK_4BYTE(a, b, c, d) \
|
||||
(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
|
||||
((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
|
||||
|
||||
#define ISPP_PACK_4BIT(a, b, c, d, e, f, g, h) \
|
||||
(((a) & 0xf) << 0 | ((b) & 0xf) << 4 | \
|
||||
((c) & 0xf) << 8 | ((d) & 0xf) << 12 | \
|
||||
((e) & 0xf) << 16 | ((f) & 0xf) << 20 | \
|
||||
((g) & 0xf) << 24 | ((h) & 0xf) << 28)
|
||||
|
||||
#define ISPP_PACK_4BYTE(a, b, c, d) \
|
||||
(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
|
||||
((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
|
||||
|
||||
#define ISPP_PACK_2SHORT(a, b) \
|
||||
(((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
|
||||
|
||||
#define ISPP_NOBIG_OVERFLOW_SIZE (2560 * 1440)
|
||||
|
||||
struct rkispp_params_vdev {
|
||||
struct rkispp_vdev_node vnode;
|
||||
struct rkispp_device *dev;
|
||||
struct rkispp_params_ops *params_ops;
|
||||
|
||||
spinlock_t config_lock;
|
||||
struct list_head params;
|
||||
struct rkispp_params_cfg *cur_params;
|
||||
struct fec_params_cfg *fec_params;
|
||||
struct rkispp_buffer *cur_buf;
|
||||
|
||||
struct v4l2_format vdev_fmt;
|
||||
@@ -32,11 +54,16 @@ struct rkispp_params_vdev {
|
||||
u32 buf_fec_idx;
|
||||
};
|
||||
|
||||
struct rkispp_params_ops {
|
||||
void (*rkispp_params_cfg)(struct rkispp_params_vdev *params_vdev, u32 frame_id);
|
||||
void (*rkispp_params_vb2_buf_queue)(struct vb2_buffer *vb);
|
||||
};
|
||||
|
||||
int rkispp_register_params_vdev(struct rkispp_device *dev);
|
||||
void rkispp_unregister_params_vdev(struct rkispp_device *dev);
|
||||
void rkispp_params_cfg(struct rkispp_params_vdev *params_vdev, u32 frame_id);
|
||||
void rkispp_params_get_fecbuf_inf(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_fecbuf_info *fecbuf);
|
||||
void rkispp_params_set_fecbuf_size(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_fecbuf_size *fecsize);
|
||||
|
||||
#endif
|
||||
|
||||
739
drivers/media/platform/rockchip/ispp/params_v10.c
Normal file
739
drivers/media/platform/rockchip/ispp/params_v10.c
Normal file
@@ -0,0 +1,739 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
|
||||
|
||||
#include <media/v4l2-common.h>
|
||||
#include <media/v4l2-ioctl.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
#include <media/videobuf2-vmalloc.h>
|
||||
#include <media/v4l2-event.h>
|
||||
#include <media/v4l2-mc.h>
|
||||
#include <linux/rkisp1-config.h>
|
||||
#include <uapi/linux/rk-video-format.h>
|
||||
#include "dev.h"
|
||||
#include "regs.h"
|
||||
|
||||
static inline size_t get_input_size(struct rkispp_params_vdev *params_vdev)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
struct rkispp_subdev *isp_sdev = &dev->ispp_sdev;
|
||||
|
||||
return isp_sdev->out_fmt.width * isp_sdev->out_fmt.height;
|
||||
}
|
||||
|
||||
|
||||
static void tnr_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_tnr_config *arg)
|
||||
{
|
||||
u32 i, val;
|
||||
|
||||
val = arg->opty_en << 2 | arg->optc_en << 3 |
|
||||
arg->gain_en << 4;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CORE_CTRL,
|
||||
SW_TNR_OPTY_EN | SW_TNR_OPTC_EN |
|
||||
SW_TNR_GLB_GAIN_EN, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->pk0_y, arg->pk1_y,
|
||||
arg->pk0_c, arg->pk1_c);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_PK0, val);
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->glb_gain_cur, arg->glb_gain_nxt);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GLB_GAIN, val);
|
||||
val = ISPP_PACK_2SHORT(arg->glb_gain_cur_div, arg->glb_gain_cur_sqrt);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GLB_GAIN_DIV, val);
|
||||
|
||||
for (i = 0; i < TNR_SIGMA_CURVE_SIZE - 1; i += 2)
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_Y01 + i * 2,
|
||||
ISPP_PACK_2SHORT(arg->sigma_y[i], arg->sigma_y[i + 1]));
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_Y10, arg->sigma_y[16]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_X18,
|
||||
ISPP_PACK_4BIT(arg->sigma_x[0], arg->sigma_x[1],
|
||||
arg->sigma_x[2], arg->sigma_x[3],
|
||||
arg->sigma_x[4], arg->sigma_x[5],
|
||||
arg->sigma_x[6], arg->sigma_x[7]));
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SIG_X910,
|
||||
ISPP_PACK_4BIT(arg->sigma_x[8], arg->sigma_x[9],
|
||||
arg->sigma_x[10], arg->sigma_x[11],
|
||||
arg->sigma_x[12], arg->sigma_x[13],
|
||||
arg->sigma_x[14], arg->sigma_x[15]));
|
||||
|
||||
for (i = 0; i < TNR_LUMA_CURVE_SIZE; i += 2) {
|
||||
val = ISPP_PACK_2SHORT(arg->luma_curve[i], arg->luma_curve[i + 1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_LUMACURVE_Y01 + i * 2, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->txt_th0_y, arg->txt_th1_y);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_Y, val);
|
||||
val = ISPP_PACK_2SHORT(arg->txt_th0_c, arg->txt_th1_c);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_C, val);
|
||||
val = ISPP_PACK_2SHORT(arg->txt_thy_dlt, arg->txt_thc_dlt);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_TH_DLT, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y0[0], arg->gfcoef_y0[1],
|
||||
arg->gfcoef_y0[2], arg->gfcoef_y0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y0[4], arg->gfcoef_y0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y1[0], arg->gfcoef_y1[1],
|
||||
arg->gfcoef_y1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y2[0], arg->gfcoef_y2[1],
|
||||
arg->gfcoef_y2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_y3[0], arg->gfcoef_y3[1],
|
||||
arg->gfcoef_y3[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_Y3, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg0[0], arg->gfcoef_yg0[1],
|
||||
arg->gfcoef_yg0[2], arg->gfcoef_yg0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg0[4], arg->gfcoef_yg0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg1[0], arg->gfcoef_yg1[1],
|
||||
arg->gfcoef_yg1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg2[0], arg->gfcoef_yg2[1],
|
||||
arg->gfcoef_yg2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yg3[0], arg->gfcoef_yg3[1],
|
||||
arg->gfcoef_yg3[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YG3, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl0[0], arg->gfcoef_yl0[1],
|
||||
arg->gfcoef_yl0[2], arg->gfcoef_yl0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl0[4], arg->gfcoef_yl0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl1[0], arg->gfcoef_yl1[1],
|
||||
arg->gfcoef_yl1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_yl2[0], arg->gfcoef_yl2[1],
|
||||
arg->gfcoef_yl2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_YL2, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg0[0], arg->gfcoef_cg0[1],
|
||||
arg->gfcoef_cg0[2], arg->gfcoef_cg0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg0[4], arg->gfcoef_cg0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg1[0], arg->gfcoef_cg1[1],
|
||||
arg->gfcoef_cg1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cg2[0], arg->gfcoef_cg2[1],
|
||||
arg->gfcoef_cg2[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CG2, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl0[0], arg->gfcoef_cl0[1],
|
||||
arg->gfcoef_cl0[2], arg->gfcoef_cl0[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL0_0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl0[4], arg->gfcoef_cl0[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL0_1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->gfcoef_cl1[0], arg->gfcoef_cl1[1],
|
||||
arg->gfcoef_cl1[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_GFCOEF_CL1, val);
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yg[0], arg->scale_yg[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YG01, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yg[2], arg->scale_yg[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YG23, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_yl[0], arg->scale_yl[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YL01, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_YL2, arg->scale_yl[2]);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[0], arg->scale_y2cg[0]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG0, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[1], arg->scale_y2cg[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG1, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cg[2], arg->scale_y2cg[2]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CG2, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cl[0], arg->scale_y2cl[0]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL0, val);
|
||||
val = ISPP_PACK_2SHORT(arg->scale_cl[1], arg->scale_y2cl[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL1, val);
|
||||
val = arg->scale_y2cl[2] << 16;
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_SCALE_CL2, val);
|
||||
val = ISPP_PACK_4BYTE(arg->weight_y[0], arg->weight_y[1],
|
||||
arg->weight_y[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_TNR_CORE_WEIGHT, val);
|
||||
}
|
||||
|
||||
static bool is_tnr_enable(struct rkispp_params_vdev *params_vdev)
|
||||
{
|
||||
u32 cur_en;
|
||||
|
||||
cur_en = rkispp_read(params_vdev->dev, RKISPP_TNR_CORE_CTRL);
|
||||
cur_en &= SW_TNR_EN;
|
||||
|
||||
return (!!cur_en);
|
||||
}
|
||||
|
||||
static void tnr_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
if (en && !is_tnr_enable(params_vdev))
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CTRL, 0, SW_TNR_1ST_FRM);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_TNR_CORE_CTRL, SW_TNR_EN, en);
|
||||
}
|
||||
|
||||
static void nr_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_nr_config *arg)
|
||||
{
|
||||
u32 i, val;
|
||||
u8 big_en, nobig_en, sd32_self_en = 0;
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_1SIGMA,
|
||||
arg->uvnr_gain_1sigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_OFFSET,
|
||||
arg->uvnr_gain_offset);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_gain_uvgain[0],
|
||||
arg->uvnr_gain_uvgain[1], arg->uvnr_gain_t2gen,
|
||||
arg->uvnr_gain_iso);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_GAIN_GBLGAIN, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1GEN_M3ALPHA,
|
||||
arg->uvnr_t1gen_m3alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_MODE,
|
||||
arg->uvnr_t1flt_mode);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_MSIGMA,
|
||||
arg->uvnr_t1flt_msigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_WTP,
|
||||
arg->uvnr_t1flt_wtp);
|
||||
for (i = 0; i < NR_UVNR_T1FLT_WTQ_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t1flt_wtq[i],
|
||||
arg->uvnr_t1flt_wtq[i + 1], arg->uvnr_t1flt_wtq[i + 2],
|
||||
arg->uvnr_t1flt_wtq[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T1FLT_WTQ0 + i, val);
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_M3ALPHA,
|
||||
arg->uvnr_t2gen_m3alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_MSIGMA,
|
||||
arg->uvnr_t2gen_msigma);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_WTP,
|
||||
arg->uvnr_t2gen_wtp);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t2gen_wtq[0],
|
||||
arg->uvnr_t2gen_wtq[1], arg->uvnr_t2gen_wtq[2],
|
||||
arg->uvnr_t2gen_wtq[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2GEN_WTQ, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2FLT_MSIGMA,
|
||||
arg->uvnr_t2flt_msigma);
|
||||
val = ISPP_PACK_4BYTE(arg->uvnr_t2flt_wtp,
|
||||
arg->uvnr_t2flt_wt[0], arg->uvnr_t2flt_wt[1],
|
||||
arg->uvnr_t2flt_wt[2]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_UVNR_T2FLT_WT, val);
|
||||
|
||||
val = ISPP_PACK_4BIT(arg->ynr_sgm_dx[0], arg->ynr_sgm_dx[1],
|
||||
arg->ynr_sgm_dx[2], arg->ynr_sgm_dx[3],
|
||||
arg->ynr_sgm_dx[4], arg->ynr_sgm_dx[5],
|
||||
arg->ynr_sgm_dx[6], arg->ynr_sgm_dx[7]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_SGM_DX_1_8, val);
|
||||
val = ISPP_PACK_4BIT(arg->ynr_sgm_dx[8], arg->ynr_sgm_dx[9],
|
||||
arg->ynr_sgm_dx[10], arg->ynr_sgm_dx[11],
|
||||
arg->ynr_sgm_dx[12], arg->ynr_sgm_dx[13],
|
||||
arg->ynr_sgm_dx[14], arg->ynr_sgm_dx[15]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_SGM_DX_9_16, val);
|
||||
|
||||
for (i = 0; i < NR_YNR_SGM_Y_SIZE - 1; i += 2) {
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LSGM_Y_0_1 + i * 2,
|
||||
ISPP_PACK_2SHORT(arg->ynr_lsgm_y[i], arg->ynr_lsgm_y[i + 1]));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSGM_Y_0_1 + i * 2,
|
||||
ISPP_PACK_2SHORT(arg->ynr_hsgm_y[i], arg->ynr_hsgm_y[i + 1]));
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LSGM_Y_16, arg->ynr_lsgm_y[16]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSGM_Y_16, arg->ynr_hsgm_y[16]);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lci[0], arg->ynr_lci[1],
|
||||
arg->ynr_lci[2], arg->ynr_lci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lgain_min[0], arg->ynr_lgain_min[1],
|
||||
arg->ynr_lgain_min[2], arg->ynr_lgain_min[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LGAIN_DIRE_MIN, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_IGAIN_DIRE_MAX, arg->ynr_lgain_max);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lmerge_bound, arg->ynr_lmerge_ratio, 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LMERGE, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lweit_flt[0], arg->ynr_lweit_flt[1],
|
||||
arg->ynr_lweit_flt[2], arg->ynr_lweit_flt[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LWEIT_FLT, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hlci[0], arg->ynr_hlci[1],
|
||||
arg->ynr_hlci[2], arg->ynr_hlci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HLCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lhci[0], arg->ynr_lhci[1],
|
||||
arg->ynr_lhci[2], arg->ynr_lhci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LHCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hhci[0], arg->ynr_hhci[1],
|
||||
arg->ynr_hhci[2], arg->ynr_hhci[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HHCI, val);
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hgain_sgm[0], arg->ynr_hgain_sgm[1],
|
||||
arg->ynr_hgain_sgm[2], arg->ynr_hgain_sgm[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HGAIN_SGM, val);
|
||||
|
||||
for (i = 0; i < NR_YNR_HWEIT_D_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hweit_d[i], arg->ynr_hweit_d[i + 1],
|
||||
arg->ynr_hweit_d[i + 2], arg->ynr_hweit_d[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_D0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < NR_YNR_HGRAD_Y_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_hgrad_y[i], arg->ynr_hgrad_y[i + 1],
|
||||
arg->ynr_hgrad_y[i + 2], arg->ynr_hgrad_y[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HGRAD_Y0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hweit[0], arg->ynr_hweit[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_1_2, val);
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hweit[2], arg->ynr_hweit[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HWEIT_3_4, val);
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HMAX_ADJUST, arg->ynr_hmax_adjust);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTRENGTH, arg->ynr_hstrength);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->ynr_lweit_cmp[0], arg->ynr_lweit_cmp[1], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LWEIT_CMP, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_LMAXGAIN_LV4, arg->ynr_lmaxgain_lv4);
|
||||
|
||||
for (i = 0; i < NR_YNR_HSTV_Y_SIZE - 1; i += 2) {
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_hstv_y[i], arg->ynr_hstv_y[i + 1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTV_Y_0_1 + i * 2, val);
|
||||
}
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_HSTV_Y_16, arg->ynr_hstv_y[16]);
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->ynr_st_scale[0], arg->ynr_st_scale[1]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_ST_SCALE_LV1_LV2, val);
|
||||
rkispp_write(params_vdev->dev, RKISPP_NR_YNR_ST_SCALE_LV3, arg->ynr_st_scale[2]);
|
||||
|
||||
big_en = arg->uvnr_big_en & 0x01;
|
||||
nobig_en = arg->uvnr_nobig_en & 0x01;
|
||||
if (get_input_size(params_vdev) > ISPP_NOBIG_OVERFLOW_SIZE) {
|
||||
big_en = 1;
|
||||
nobig_en = 0;
|
||||
}
|
||||
|
||||
if (params_vdev->dev->hw_dev->dev_num == 1)
|
||||
sd32_self_en = arg->uvnr_sd32_self_en;
|
||||
val = arg->uvnr_step1_en << 1 | arg->uvnr_step2_en << 2 |
|
||||
arg->nr_gain_en << 3 | sd32_self_en << 4 |
|
||||
nobig_en << 5 | big_en << 6;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_NR_UVNR_CTRL_PARA,
|
||||
SW_UVNR_STEP1_ON | SW_UVNR_STEP2_ON |
|
||||
SW_NR_GAIN_BYPASS | SW_UVNR_NOBIG_EN |
|
||||
SW_UVNR_BIG_EN, val);
|
||||
}
|
||||
|
||||
static void nr_enable(struct rkispp_params_vdev *params_vdev, bool en,
|
||||
struct rkispp_nr_config *arg)
|
||||
{
|
||||
u8 big_en, nobig_en;
|
||||
u32 val;
|
||||
|
||||
big_en = arg->uvnr_big_en & 0x01;
|
||||
nobig_en = arg->uvnr_nobig_en & 0x01;
|
||||
if (get_input_size(params_vdev) > ISPP_NOBIG_OVERFLOW_SIZE) {
|
||||
big_en = 1;
|
||||
nobig_en = 0;
|
||||
}
|
||||
|
||||
val = arg->uvnr_step1_en << 1 | arg->uvnr_step2_en << 2 |
|
||||
arg->nr_gain_en << 3 | nobig_en << 5 | big_en << 6;
|
||||
|
||||
if (en)
|
||||
val |= SW_NR_EN;
|
||||
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_NR_UVNR_CTRL_PARA,
|
||||
SW_UVNR_STEP1_ON | SW_UVNR_STEP2_ON |
|
||||
SW_NR_GAIN_BYPASS | SW_UVNR_NOBIG_EN |
|
||||
SW_UVNR_BIG_EN | SW_NR_EN, val);
|
||||
}
|
||||
|
||||
static void shp_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_sharp_config *arg)
|
||||
{
|
||||
u32 i, val;
|
||||
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CTRL,
|
||||
SW_SHP_WR_ROT_MODE(3),
|
||||
SW_SHP_WR_ROT_MODE(arg->rotation));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_SC_DOWN,
|
||||
(arg->scl_down_v & 0x1) << 1 | (arg->scl_down_h & 0x1));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_TILE_IDX,
|
||||
(arg->tile_ycnt & 0x1F) << 8 | (arg->tile_xcnt & 0xFF));
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_FACTOR, arg->hbf_ratio |
|
||||
arg->ehf_th << 16 | arg->pbf_ratio << 24);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_TH, arg->edge_thed |
|
||||
arg->dir_min << 8 | arg->smoth_th4 << 16);
|
||||
val = ISPP_PACK_2SHORT(arg->l_alpha, arg->g_alpha);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_ALPHA, val);
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_k[0], arg->pbf_k[1], arg->pbf_k[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_PBF_KERNEL, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mrf_k[0], arg->mrf_k[1], arg->mrf_k[2], arg->mrf_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MRF_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mrf_k[4], arg->mrf_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MRF_KERNEL1, val);
|
||||
|
||||
for (i = 0; i < SHP_MBF_KERNEL_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->mbf_k[i], arg->mbf_k[i + 1],
|
||||
arg->mbf_k[i + 2], arg->mbf_k[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MBF_KERNEL0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->hrf_k[0], arg->hrf_k[1], arg->hrf_k[2], arg->hrf_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HRF_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hrf_k[4], arg->hrf_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HRF_KERNEL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hbf_k[0], arg->hbf_k[1], arg->hbf_k[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_KERNEL, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->eg_coef[0], arg->eg_coef[1], arg->eg_coef[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_COEF, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_smoth[0], arg->eg_smoth[1], arg->eg_smoth[2], 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_SMOTH, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_gaus[0], arg->eg_gaus[1], arg->eg_gaus[2], arg->eg_gaus[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_GAUS0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->eg_gaus[4], arg->eg_gaus[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_GAUS1, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->dog_k[0], arg->dog_k[1], arg->dog_k[2], arg->dog_k[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DOG_KERNEL0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->dog_k[4], arg->dog_k[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DOG_KERNEL1, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_point[0], arg->lum_point[1],
|
||||
arg->lum_point[2], arg->lum_point[3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_POINT0, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_point[4], arg->lum_point[5], 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_POINT1, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_shf_bits, arg->mbf_shf_bits, arg->hbf_shf_bits, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_SHF_BITS, val);
|
||||
|
||||
for (i = 0; i < SHP_SIGMA_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->pbf_sigma[i], arg->pbf_sigma[i + 1],
|
||||
arg->pbf_sigma[i + 2], arg->pbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_PBF_SIGMA_INV0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->mbf_sigma[i], arg->mbf_sigma[i + 1],
|
||||
arg->mbf_sigma[i + 2], arg->mbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_MBF_SIGMA_INV0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->hbf_sigma[i], arg->hbf_sigma[i + 1],
|
||||
arg->hbf_sigma[i + 2], arg->hbf_sigma[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_HBF_SIGMA_INV0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_LUM_CLP_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->lum_clp_m[i], arg->lum_clp_m[i + 1],
|
||||
arg->lum_clp_m[i + 2], arg->lum_clp_m[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_CLP_M0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->lum_clp_h[i], arg->lum_clp_h[i + 1],
|
||||
arg->lum_clp_h[i + 2], arg->lum_clp_h[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_CLP_H0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_LUM_MIN_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->lum_min_m[i], arg->lum_min_m[i + 1],
|
||||
arg->lum_min_m[i + 2], arg->lum_min_m[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_LUM_MIN_M0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_EDGE_LUM_THED_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->edge_lum_thed[i], arg->edge_lum_thed[i + 1],
|
||||
arg->edge_lum_thed[i + 2], arg->edge_lum_thed[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_EDGE_LUM_THED0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_CLAMP_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->clamp_pos[i], arg->clamp_pos[i + 1],
|
||||
arg->clamp_pos[i + 2], arg->clamp_pos[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_CLAMP_POS_DOG0 + i, val);
|
||||
val = ISPP_PACK_4BYTE(arg->clamp_neg[i], arg->clamp_neg[i + 1],
|
||||
arg->clamp_neg[i + 2], arg->clamp_neg[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_CLAMP_NEG_DOG0 + i, val);
|
||||
}
|
||||
|
||||
for (i = 0; i < SHP_DETAIL_ALPHA_SIZE; i += 4) {
|
||||
val = ISPP_PACK_4BYTE(arg->detail_alpha[i], arg->detail_alpha[i + 1],
|
||||
arg->detail_alpha[i + 2], arg->detail_alpha[i + 3]);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_DETAIL_ALPHA_DOG0 + i, val);
|
||||
}
|
||||
|
||||
val = ISPP_PACK_2SHORT(arg->rfl_ratio, arg->rfh_ratio);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_RF_RATIO, val);
|
||||
|
||||
val = ISPP_PACK_4BYTE(arg->m_ratio, arg->h_ratio, 0, 0);
|
||||
rkispp_write(params_vdev->dev, RKISPP_SHARP_GRAD_RATIO, val);
|
||||
|
||||
val = arg->alpha_adp_en << 1 | arg->yin_flt_en << 3 |
|
||||
arg->edge_avg_en << 4;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CORE_CTRL,
|
||||
SW_SHP_ALPHA_ADP_EN | SW_SHP_YIN_FLT_EN |
|
||||
SW_SHP_EDGE_AVG_EN, val);
|
||||
}
|
||||
|
||||
static void shp_enable(struct rkispp_params_vdev *params_vdev, bool en,
|
||||
struct rkispp_sharp_config *arg)
|
||||
{
|
||||
u32 ens = params_vdev->dev->stream_vdev.module_ens;
|
||||
u32 val;
|
||||
|
||||
if (en && !(ens & ISPP_MODULE_FEC)) {
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL0_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL1_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SCL2_CTRL,
|
||||
SW_SCL_FIRST_MODE, SW_SCL_FIRST_MODE);
|
||||
} else {
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL0_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL1_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL2_CTRL, SW_SCL_FIRST_MODE);
|
||||
}
|
||||
|
||||
val = arg->alpha_adp_en << 1 | arg->yin_flt_en << 3 |
|
||||
arg->edge_avg_en << 4;
|
||||
if (en)
|
||||
val |= SW_SHP_EN;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_SHARP_CORE_CTRL,
|
||||
SW_SHP_ALPHA_ADP_EN | SW_SHP_YIN_FLT_EN |
|
||||
SW_SHP_EDGE_AVG_EN | SW_SHP_EN, val);
|
||||
}
|
||||
|
||||
static void fec_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_fec_config *arg)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
struct rkispp_fec_head *fec_data;
|
||||
u32 width, height, mesh_size;
|
||||
dma_addr_t dma_addr;
|
||||
u32 val, i, buf_idx;
|
||||
|
||||
width = dev->ispp_sdev.out_fmt.width;
|
||||
height = dev->ispp_sdev.out_fmt.height;
|
||||
mesh_size = cal_fec_mesh(width, height, 0);
|
||||
if (arg->mesh_size > mesh_size) {
|
||||
v4l2_err(&dev->v4l2_dev,
|
||||
"Input mesh size too large. mesh size 0x%x, 0x%x\n",
|
||||
arg->mesh_size, mesh_size);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (arg->buf_fd == params_vdev->buf_fec[i].dma_fd)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_MESH_BUF_NUM) {
|
||||
dev_err(dev->dev, "cannot find fec buf fd(%d)\n", arg->buf_fd);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!params_vdev->buf_fec[i].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_INIT;
|
||||
|
||||
buf_idx = i;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_CHIPINUSE;
|
||||
params_vdev->buf_fec_idx = buf_idx;
|
||||
|
||||
rkispp_prepare_buffer(dev, ¶ms_vdev->buf_fec[buf_idx]);
|
||||
|
||||
dma_addr = params_vdev->buf_fec[buf_idx].dma_addr;
|
||||
val = dma_addr + fec_data->meshxf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshyf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshxi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XINT_BASE, val);
|
||||
val = dma_addr + fec_data->meshyi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YINT_BASE, val);
|
||||
|
||||
val = 0;
|
||||
if (arg->mesh_density)
|
||||
val = SW_MESH_DENSITY;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_MESH_DENSITY, val);
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_SIZE, arg->mesh_size);
|
||||
|
||||
val = (arg->crop_height & 0x1FFFF) << 14 |
|
||||
(arg->crop_width & 0x1FFFF) << 1 | (arg->crop_en & 0x01);
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_CROP, val);
|
||||
}
|
||||
|
||||
static void fec_data_abandon(struct rkispp_params_vdev *vdev,
|
||||
struct rkispp_params_cfg *params)
|
||||
{
|
||||
struct rkispp_fec_head *data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (params->fec_cfg.buf_fd == vdev->buf_fec[i].dma_fd) {
|
||||
data = (struct rkispp_fec_head *)vdev->buf_fec[i].vaddr;
|
||||
if (data)
|
||||
data->stat = FEC_BUF_INIT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void fec_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
u32 buf_idx;
|
||||
|
||||
if (en) {
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
if (!params_vdev->buf_fec[buf_idx].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL0_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL1_CTRL, SW_SCL_FIRST_MODE);
|
||||
rkispp_clear_bits(params_vdev->dev, RKISPP_SCL2_CTRL, SW_SCL_FIRST_MODE);
|
||||
}
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_FEC_EN, en);
|
||||
}
|
||||
|
||||
static void orb_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct rkispp_orb_config *arg)
|
||||
{
|
||||
rkispp_write(params_vdev->dev, RKISPP_ORB_LIMIT_VALUE, arg->limit_value & 0xFF);
|
||||
rkispp_write(params_vdev->dev, RKISPP_ORB_MAX_FEATURE, arg->max_feature & 0x1FFFFF);
|
||||
}
|
||||
|
||||
static void orb_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_ORB_CORE_CTRL, SW_ORB_EN, en);
|
||||
}
|
||||
|
||||
static void rkispp_params_cfg(struct rkispp_params_vdev *params_vdev, u32 frame_id)
|
||||
{
|
||||
struct rkispp_params_cfg *new_params = NULL;
|
||||
u32 module_en_update, module_cfg_update, module_ens;
|
||||
|
||||
spin_lock(¶ms_vdev->config_lock);
|
||||
if (!params_vdev->streamon) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
/* get buffer by frame_id */
|
||||
while (!list_empty(¶ms_vdev->params) && !params_vdev->cur_buf) {
|
||||
params_vdev->cur_buf = list_first_entry(¶ms_vdev->params,
|
||||
struct rkispp_buffer, queue);
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
if (new_params->frame_id < frame_id) {
|
||||
if (new_params->module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_data_abandon(params_vdev, new_params);
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
continue;
|
||||
} else if (new_params->frame_id == frame_id) {
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
} else {
|
||||
params_vdev->cur_buf = NULL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!params_vdev->cur_buf) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
|
||||
module_en_update = new_params->module_en_update;
|
||||
module_cfg_update = new_params->module_cfg_update;
|
||||
module_ens = new_params->module_ens;
|
||||
if (params_vdev->dev->hw_dev->is_fec_ext) {
|
||||
module_en_update &= ~ISPP_MODULE_FEC;
|
||||
module_cfg_update &= ~ISPP_MODULE_FEC;
|
||||
module_ens &= ~ISPP_MODULE_FEC;
|
||||
}
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_TNR)
|
||||
tnr_config(params_vdev,
|
||||
&new_params->tnr_cfg);
|
||||
if (module_en_update & ISPP_MODULE_TNR)
|
||||
tnr_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_TNR));
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_NR)
|
||||
nr_config(params_vdev,
|
||||
&new_params->nr_cfg);
|
||||
if (module_en_update & ISPP_MODULE_NR)
|
||||
nr_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_NR),
|
||||
&new_params->nr_cfg);
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_SHP)
|
||||
shp_config(params_vdev,
|
||||
&new_params->shp_cfg);
|
||||
if (module_en_update & ISPP_MODULE_SHP)
|
||||
shp_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_SHP),
|
||||
&new_params->shp_cfg);
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_config(params_vdev,
|
||||
&new_params->fec_cfg);
|
||||
if (module_en_update & ISPP_MODULE_FEC)
|
||||
fec_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_FEC));
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_ORB)
|
||||
orb_config(params_vdev,
|
||||
&new_params->orb_cfg);
|
||||
if (module_en_update & ISPP_MODULE_ORB)
|
||||
orb_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_ORB));
|
||||
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf,
|
||||
VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
}
|
||||
|
||||
|
||||
static void params_vb2_buf_queue(struct vb2_buffer *vb)
|
||||
{
|
||||
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
|
||||
struct rkispp_buffer *params_buf = to_rkispp_buffer(vbuf);
|
||||
struct vb2_queue *vq = vb->vb2_queue;
|
||||
struct rkispp_params_vdev *params_vdev = vq->drv_priv;
|
||||
struct rkispp_stream_vdev *stream_vdev = ¶ms_vdev->dev->stream_vdev;
|
||||
struct rkispp_params_cfg *new_params;
|
||||
unsigned long flags;
|
||||
|
||||
new_params = (struct rkispp_params_cfg *)vb2_plane_vaddr(vb, 0);
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
if (params_vdev->first_params) {
|
||||
params_vdev->first_params = false;
|
||||
if (new_params->module_init_ens) {
|
||||
if (params_vdev->dev->hw_dev->is_fec_ext)
|
||||
new_params->module_init_ens &= ~ISPP_MODULE_FEC_ST;
|
||||
stream_vdev->module_ens = new_params->module_init_ens;
|
||||
|
||||
}
|
||||
wake_up(¶ms_vdev->dev->sync_onoff);
|
||||
}
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
|
||||
new_params->module_init_ens = stream_vdev->module_ens;
|
||||
params_buf->vaddr[0] = new_params;
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
list_add_tail(¶ms_buf->queue, ¶ms_vdev->params);
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
}
|
||||
|
||||
static struct rkispp_params_ops rkispp_params_ops = {
|
||||
.rkispp_params_cfg = rkispp_params_cfg,
|
||||
.rkispp_params_vb2_buf_queue = params_vb2_buf_queue,
|
||||
};
|
||||
|
||||
void rkispp_params_init_ops_v10(struct rkispp_params_vdev *params_vdev)
|
||||
{
|
||||
params_vdev->params_ops = &rkispp_params_ops;
|
||||
}
|
||||
209
drivers/media/platform/rockchip/ispp/params_v20.c
Normal file
209
drivers/media/platform/rockchip/ispp/params_v20.c
Normal file
@@ -0,0 +1,209 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
|
||||
|
||||
#include <media/v4l2-common.h>
|
||||
#include <media/v4l2-ioctl.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
#include <media/videobuf2-vmalloc.h>
|
||||
#include <media/v4l2-event.h>
|
||||
#include <media/v4l2-mc.h>
|
||||
#include <uapi/linux/rk-video-format.h>
|
||||
#include "dev.h"
|
||||
#include "regs.h"
|
||||
|
||||
static void fec_enable(struct rkispp_params_vdev *params_vdev, bool en)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
u32 buf_idx;
|
||||
|
||||
if (en) {
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
if (!params_vdev->buf_fec[buf_idx].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_FEC_EN, en);
|
||||
}
|
||||
|
||||
static void fec_config(struct rkispp_params_vdev *params_vdev,
|
||||
struct fec_config *arg)
|
||||
{
|
||||
struct rkispp_device *dev = params_vdev->dev;
|
||||
struct rkispp_fec_head *fec_data;
|
||||
u32 width, height, mesh_size;
|
||||
dma_addr_t dma_addr;
|
||||
u32 val, i, buf_idx;
|
||||
|
||||
width = dev->ispp_sdev.out_fmt.width;
|
||||
height = dev->ispp_sdev.out_fmt.height;
|
||||
mesh_size = cal_fec_mesh(width, height, 1);
|
||||
if (arg->mesh_size > mesh_size) {
|
||||
v4l2_err(&dev->v4l2_dev,
|
||||
"Input mesh size too large. mesh size 0x%x, 0x%x\n",
|
||||
arg->mesh_size, mesh_size);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (arg->buf_fd == params_vdev->buf_fec[i].dma_fd)
|
||||
break;
|
||||
}
|
||||
if (i == FEC_MESH_BUF_NUM) {
|
||||
dev_err(dev->dev, "cannot find fec buf fd(%d)\n", arg->buf_fd);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!params_vdev->buf_fec[i].vaddr) {
|
||||
dev_err(dev->dev, "no fec buffer allocated\n");
|
||||
return;
|
||||
}
|
||||
|
||||
buf_idx = params_vdev->buf_fec_idx;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_INIT;
|
||||
|
||||
buf_idx = i;
|
||||
fec_data = (struct rkispp_fec_head *)params_vdev->buf_fec[buf_idx].vaddr;
|
||||
fec_data->stat = FEC_BUF_CHIPINUSE;
|
||||
params_vdev->buf_fec_idx = buf_idx;
|
||||
|
||||
rkispp_prepare_buffer(dev, ¶ms_vdev->buf_fec[buf_idx]);
|
||||
|
||||
dma_addr = params_vdev->buf_fec[buf_idx].dma_addr;
|
||||
val = dma_addr + fec_data->meshxf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshyf_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YFRA_BASE, val);
|
||||
val = dma_addr + fec_data->meshxi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_XINT_BASE, val);
|
||||
val = dma_addr + fec_data->meshyi_oft;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_YINT_BASE, val);
|
||||
|
||||
val = 0;
|
||||
if (arg->mesh_density)
|
||||
val = SW_MESH_DENSITY;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_MESH_DENSITY, val);
|
||||
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_MESH_SIZE, arg->mesh_size);
|
||||
|
||||
val = arg->dst_width << 16 | arg->dst_height;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_DST_SIZE, val);
|
||||
|
||||
val = arg->src_width << 16 | arg->src_height;
|
||||
rkispp_write(params_vdev->dev, RKISPP_FEC_SRC_SIZE, val);
|
||||
|
||||
val = arg->fec_bic_mode;
|
||||
rkispp_set_bits(params_vdev->dev, RKISPP_FEC_CORE_CTRL, SW_BIC_MODE, val);
|
||||
}
|
||||
|
||||
static void fec_data_abandon(struct rkispp_params_vdev *vdev,
|
||||
struct fec_params_cfg *params)
|
||||
{
|
||||
struct rkispp_fec_head *data;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < FEC_MESH_BUF_NUM; i++) {
|
||||
if (params->fec_cfg.buf_fd == vdev->buf_fec[i].dma_fd) {
|
||||
data = (struct rkispp_fec_head *)vdev->buf_fec[i].vaddr;
|
||||
if (data)
|
||||
data->stat = FEC_BUF_INIT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void rkispp_params_cfg(struct rkispp_params_vdev *params_vdev, u32 frame_id)
|
||||
{
|
||||
struct fec_params_cfg *new_params = NULL;
|
||||
u32 module_en_update, module_cfg_update, module_ens;
|
||||
|
||||
spin_lock(¶ms_vdev->config_lock);
|
||||
if (!params_vdev->streamon) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
/* get buffer by frame_id */
|
||||
while (!list_empty(¶ms_vdev->params) && !params_vdev->cur_buf) {
|
||||
params_vdev->cur_buf = list_first_entry(¶ms_vdev->params,
|
||||
struct rkispp_buffer, queue);
|
||||
|
||||
new_params = (struct fec_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
if (new_params->frame_id < frame_id) {
|
||||
if (new_params->module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_data_abandon(params_vdev, new_params);
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
continue;
|
||||
} else if (new_params->frame_id == frame_id) {
|
||||
list_del(¶ms_vdev->cur_buf->queue);
|
||||
} else {
|
||||
params_vdev->cur_buf = NULL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (!params_vdev->cur_buf) {
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
new_params = (struct fec_params_cfg *)(params_vdev->cur_buf->vaddr[0]);
|
||||
|
||||
module_en_update = new_params->module_en_update;
|
||||
module_cfg_update = new_params->module_cfg_update;
|
||||
module_ens = new_params->module_ens;
|
||||
if (params_vdev->dev->hw_dev->is_fec_ext) {
|
||||
module_en_update &= ~ISPP_MODULE_FEC;
|
||||
module_cfg_update &= ~ISPP_MODULE_FEC;
|
||||
module_ens &= ~ISPP_MODULE_FEC;
|
||||
}
|
||||
|
||||
|
||||
if (module_cfg_update & ISPP_MODULE_FEC)
|
||||
fec_config(params_vdev,
|
||||
&new_params->fec_cfg);
|
||||
if (module_en_update & ISPP_MODULE_FEC)
|
||||
fec_enable(params_vdev,
|
||||
!!(module_ens & ISPP_MODULE_FEC));
|
||||
|
||||
vb2_buffer_done(¶ms_vdev->cur_buf->vb.vb2_buf,
|
||||
VB2_BUF_STATE_DONE);
|
||||
params_vdev->cur_buf = NULL;
|
||||
|
||||
spin_unlock(¶ms_vdev->config_lock);
|
||||
}
|
||||
|
||||
static void params_vb2_buf_queue(struct vb2_buffer *vb)
|
||||
{
|
||||
struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
|
||||
struct rkispp_buffer *params_buf = to_rkispp_buffer(vbuf);
|
||||
struct vb2_queue *vq = vb->vb2_queue;
|
||||
struct rkispp_params_vdev *params_vdev = vq->drv_priv;
|
||||
struct fec_params_cfg *new_params;
|
||||
unsigned long flags;
|
||||
|
||||
new_params = (struct fec_params_cfg *)vb2_plane_vaddr(vb, 0);
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
if (params_vdev->first_params) {
|
||||
params_vdev->first_params = false;
|
||||
wake_up(¶ms_vdev->dev->sync_onoff);
|
||||
}
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
params_buf->vaddr[0] = new_params;
|
||||
spin_lock_irqsave(¶ms_vdev->config_lock, flags);
|
||||
list_add_tail(¶ms_buf->queue, ¶ms_vdev->params);
|
||||
spin_unlock_irqrestore(¶ms_vdev->config_lock, flags);
|
||||
}
|
||||
|
||||
static struct rkispp_params_ops rkispp_params_ops = {
|
||||
.rkispp_params_cfg = rkispp_params_cfg,
|
||||
.rkispp_params_vb2_buf_queue = params_vb2_buf_queue,
|
||||
};
|
||||
|
||||
void rkispp_params_init_ops_v20(struct rkispp_params_vdev *params_vdev)
|
||||
{
|
||||
params_vdev->params_ops = &rkispp_params_ops;
|
||||
}
|
||||
@@ -314,11 +314,13 @@
|
||||
#define RKISPP_FEC_MESH_YFRA_BASE_SHD (RKISPP_FEC + 0x0040)
|
||||
#define RKISPP_FEC_WR_Y_BASE_SHD (RKISPP_FEC + 0x0044)
|
||||
#define RKISPP_FEC_WR_UV_BASE_SHD (RKISPP_FEC + 0x0048)
|
||||
#define RKISPP_FEC_FBCE_HEAD_OFFSET (RKISPP_FEC + 0x0050)
|
||||
#define RKISPP_FEC_CORE_CTRL (RKISPP_FEC + 0x0080)
|
||||
#define RKISPP_FEC_PIC_SIZE (RKISPP_FEC + 0x0088)
|
||||
#define RKISPP_FEC_DST_SIZE (RKISPP_FEC + 0x0088)
|
||||
#define RKISPP_FEC_MESH_SIZE (RKISPP_FEC + 0x008C)
|
||||
#define RKISPP_FEC_DMA_STATUS (RKISPP_FEC + 0x0090)
|
||||
#define RKISPP_FEC_CROP (RKISPP_FEC + 0x0094)
|
||||
#define RKISPP_FEC_SRC_SIZE (RKISPP_FEC + 0x0098)
|
||||
|
||||
#define FMT_WR_MASK GENMASK(7, 4)
|
||||
#define FMT_RD_MASK GENMASK(3, 0)
|
||||
@@ -507,9 +509,11 @@
|
||||
|
||||
/* FEC_CORE_CTRL */
|
||||
#define SW_FEC_EN_SHD BIT(31)
|
||||
#define SW_OFFSET_ENABLE BIT(31)
|
||||
#define SW_MINBUF_NON_UPDATE_SHD BIT(30)
|
||||
#define SW_MINBUF_NON_UPDATE BIT(6)
|
||||
#define SW_MESH_DENSITY BIT(5)
|
||||
#define SW_BIC_MODE GENMASK(4, 3)
|
||||
#define SW_FEC2DDR_DIS BIT(1)
|
||||
#define SW_FEC_EN BIT(0)
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -5,6 +5,7 @@
|
||||
#define _RKISPP_STREAM_H
|
||||
|
||||
#include "common.h"
|
||||
#include "params.h"
|
||||
|
||||
struct rkispp_stream;
|
||||
|
||||
@@ -121,7 +122,9 @@ struct nr_module {
|
||||
|
||||
struct fec_module {
|
||||
struct list_head list_rd;
|
||||
struct rkispp_dummy_buffer *cur_rd;
|
||||
struct list_head list_wr;
|
||||
struct rkisp_ispp_buf *cur_rd;
|
||||
struct rkispp_dummy_buffer *dummy_cur_rd;
|
||||
struct rkisp_ispp_reg *reg_buf;
|
||||
struct frame_debug_info dbg;
|
||||
spinlock_t buf_lock;
|
||||
@@ -200,6 +203,21 @@ struct rkispp_monitor {
|
||||
bool is_en;
|
||||
};
|
||||
|
||||
|
||||
struct rkispp_stream_ops {
|
||||
int (*config_modules)(struct rkispp_device *dev);
|
||||
void (*destroy_buf)(struct rkispp_stream *stream);
|
||||
void (*fec_work_event)(struct rkispp_device *dev, void *buf_rd,
|
||||
bool is_isr, bool is_quick);
|
||||
int (*start_isp)(struct rkispp_device *dev);
|
||||
void (*check_to_force_update)(struct rkispp_device *dev, u32 mis_val);
|
||||
void (*update_mi)(struct rkispp_stream *stream);
|
||||
enum hrtimer_restart (*rkispp_frame_done_early)(struct hrtimer *timer);
|
||||
void (*rkispp_module_work_event)(struct rkispp_device *dev,
|
||||
void *buf_rd, void *buf_wr,
|
||||
u32 module, bool is_isr);
|
||||
};
|
||||
|
||||
struct rkispp_vir_cpy {
|
||||
struct work_struct work;
|
||||
struct completion cmpl;
|
||||
@@ -216,6 +234,7 @@ struct rkispp_stream_vdev {
|
||||
struct fec_module fec;
|
||||
struct frame_debug_info dbg;
|
||||
struct rkispp_monitor monitor;
|
||||
struct rkispp_stream_ops *stream_ops;
|
||||
struct rkispp_vir_cpy vir_cpy;
|
||||
struct rkisp_ispp_buf input[VIDEO_MAX_FRAME];
|
||||
struct hrtimer fec_qst;
|
||||
@@ -232,10 +251,30 @@ void rkispp_sendbuf_to_nr(struct rkispp_device *dev,
|
||||
struct rkispp_tnr_inf *tnr_inf);
|
||||
void rkispp_set_trigger_mode(struct rkispp_device *dev,
|
||||
struct rkispp_trigger_mode *mode);
|
||||
void rkispp_module_work_event(struct rkispp_device *dev,
|
||||
void *buf_rd, void *buf_wr,
|
||||
u32 module, bool is_isr);
|
||||
void rkispp_isr(u32 mis_val, struct rkispp_device *dev);
|
||||
void rkispp_unregister_stream_vdevs(struct rkispp_device *dev);
|
||||
int rkispp_register_stream_vdevs(struct rkispp_device *dev);
|
||||
void *get_pool_buf(struct rkispp_device *dev, struct rkisp_ispp_buf *dbufs);
|
||||
void *dbuf_to_dummy(struct dma_buf *dbuf, struct rkispp_dummy_buffer *pool, int num);
|
||||
void *get_list_buf(struct list_head *list, bool is_isp_ispp);
|
||||
void get_stream_buf(struct rkispp_stream *stream);
|
||||
void secure_config_mb(struct rkispp_stream *stream);
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V10)
|
||||
void rkispp_stream_init_ops_v10(struct rkispp_stream_vdev *stream_vdev);
|
||||
void rkispp_params_init_ops_v10(struct rkispp_params_vdev *params_vdev);
|
||||
#else
|
||||
static inline void rkispp_stream_init_ops_v10(struct rkispp_stream_vdev *stream_vdev) {}
|
||||
static inline void rkispp_params_init_ops_v10(struct rkispp_params_vdev *params_vdev) {}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISPP_VERSION_V20)
|
||||
void rkispp_stream_init_ops_v20(struct rkispp_stream_vdev *stream_vdev);
|
||||
void rkispp_params_init_ops_v20(struct rkispp_params_vdev *params_vdev);
|
||||
#else
|
||||
static inline void rkispp_stream_init_ops_v20(struct rkispp_stream_vdev *stream_vdev) {}
|
||||
static inline void rkispp_params_init_ops_v20(struct rkispp_params_vdev *params_vdev) {}
|
||||
#endif
|
||||
int rkispp_frame_end(struct rkispp_stream *stream, u32 state);
|
||||
void rkispp_start_3a_run(struct rkispp_device *dev);
|
||||
#endif
|
||||
|
||||
1733
drivers/media/platform/rockchip/ispp/stream_v10.c
Normal file
1733
drivers/media/platform/rockchip/ispp/stream_v10.c
Normal file
File diff suppressed because it is too large
Load Diff
464
drivers/media/platform/rockchip/ispp/stream_v20.c
Normal file
464
drivers/media/platform/rockchip/ispp/stream_v20.c
Normal file
@@ -0,0 +1,464 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
#include <media/v4l2-common.h>
|
||||
#include <media/v4l2-event.h>
|
||||
#include <media/v4l2-fh.h>
|
||||
#include <media/v4l2-ioctl.h>
|
||||
#include <media/v4l2-mc.h>
|
||||
#include <media/v4l2-subdev.h>
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
#include <media/videobuf2-dma-sg.h>
|
||||
#include <linux/rkisp1-config.h>
|
||||
|
||||
#include "dev.h"
|
||||
#include "regs.h"
|
||||
|
||||
static void set_y_addr(struct rkispp_stream *stream, u32 val)
|
||||
{
|
||||
rkispp_write(stream->isppdev, stream->config->reg.cur_y_base, val);
|
||||
}
|
||||
|
||||
static void set_uv_addr(struct rkispp_stream *stream, u32 val)
|
||||
{
|
||||
rkispp_write(stream->isppdev, stream->config->reg.cur_uv_base, val);
|
||||
}
|
||||
|
||||
|
||||
static void update_mi(struct rkispp_stream *stream)
|
||||
{
|
||||
struct rkispp_device *dev = stream->isppdev;
|
||||
struct rkispp_dummy_buffer *dummy_buf;
|
||||
u32 val;
|
||||
|
||||
if (stream->curr_buf) {
|
||||
val = stream->curr_buf->buff_addr[RKISPP_PLANE_Y];
|
||||
set_y_addr(stream, val);
|
||||
val = stream->curr_buf->buff_addr[RKISPP_PLANE_UV];
|
||||
set_uv_addr(stream, val);
|
||||
}
|
||||
|
||||
if (stream->type == STREAM_OUTPUT && !stream->curr_buf) {
|
||||
dummy_buf = &dev->hw_dev->dummy_buf;
|
||||
set_y_addr(stream, dummy_buf->dma_addr);
|
||||
set_uv_addr(stream, dummy_buf->dma_addr);
|
||||
}
|
||||
|
||||
v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
|
||||
"%s stream:%d Y:0x%x UV:0x%x\n",
|
||||
__func__, stream->id,
|
||||
rkispp_read(dev, stream->config->reg.cur_y_base),
|
||||
rkispp_read(dev, stream->config->reg.cur_uv_base));
|
||||
}
|
||||
|
||||
static int config_fec(struct rkispp_device *dev)
|
||||
{
|
||||
struct rkispp_stream_vdev *vdev;
|
||||
struct rkispp_stream *stream = NULL;
|
||||
struct rkispp_fec_head *fec_data;
|
||||
struct rkispp_hw_dev *hw = dev->hw_dev;
|
||||
u32 fmt, mult = 1, mesh_size;
|
||||
u32 in_width, in_height;
|
||||
u32 addr_offs, max_w, max_h;
|
||||
u32 addryf, addrxf, addryi, addrxi;
|
||||
|
||||
vdev = &dev->stream_vdev;
|
||||
vdev->fec.is_end = true;
|
||||
if (!(vdev->module_ens & ISPP_MODULE_FEC))
|
||||
return 0;
|
||||
|
||||
if (dev->inp == INP_DDR) {
|
||||
stream = &vdev->stream[STREAM_II];
|
||||
fmt = stream->out_cap_fmt.wr_fmt;
|
||||
} else {
|
||||
fmt = FMT_YUV422;
|
||||
}
|
||||
|
||||
in_width = dev->ispp_sdev.in_fmt.width;
|
||||
in_height = dev->ispp_sdev.in_fmt.height;
|
||||
max_w = hw->max_in.w ? hw->max_in.w : in_width;
|
||||
max_h = hw->max_in.h ? hw->max_in.h : in_height;
|
||||
addr_offs = max_w * max_h;
|
||||
vdev->fec.uv_offset = addr_offs;
|
||||
|
||||
if (stream) {
|
||||
stream->config->frame_end_id = FEC_INT;
|
||||
stream->config->reg.cur_y_base = RKISPP_FEC_RD_Y_BASE;
|
||||
stream->config->reg.cur_uv_base = RKISPP_FEC_RD_UV_BASE;
|
||||
stream->config->reg.cur_y_base_shd = RKISPP_FEC_RD_Y_BASE_SHD;
|
||||
stream->config->reg.cur_uv_base_shd = RKISPP_FEC_RD_UV_BASE_SHD;
|
||||
}
|
||||
|
||||
|
||||
if (fmt & FMT_YUYV)
|
||||
mult = 2;
|
||||
rkispp_set_bits(dev, RKISPP_FEC_CTRL, FMT_RD_MASK, fmt);
|
||||
|
||||
rkispp_write(dev, RKISPP_FEC_RD_VIR_STRIDE, ALIGN(in_width * mult, 16) >> 2);
|
||||
rkispp_write(dev, RKISPP_FEC_SRC_SIZE, in_height << 16 | in_width);
|
||||
|
||||
fec_data = (struct rkispp_fec_head *)dev->params_vdev.buf_fec[0].vaddr;
|
||||
if (fec_data) {
|
||||
rkispp_prepare_buffer(dev, &dev->params_vdev.buf_fec[0]);
|
||||
addrxf =
|
||||
dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshxf_oft;
|
||||
addryf =
|
||||
dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshyf_oft;
|
||||
addrxi =
|
||||
dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshxi_oft;
|
||||
addryi =
|
||||
dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshyi_oft;
|
||||
rkispp_write(dev, RKISPP_FEC_MESH_XFRA_BASE, addrxf);
|
||||
rkispp_write(dev, RKISPP_FEC_MESH_YFRA_BASE, addryf);
|
||||
rkispp_write(dev, RKISPP_FEC_MESH_XINT_BASE, addrxi);
|
||||
rkispp_write(dev, RKISPP_FEC_MESH_YINT_BASE, addryi);
|
||||
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (stream->out_fmt.width > 1920) {
|
||||
mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 1);
|
||||
rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, SW_MESH_DENSITY);
|
||||
} else {
|
||||
mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 0);
|
||||
rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, 0);
|
||||
}
|
||||
rkispp_write(dev, RKISPP_FEC_MESH_SIZE, mesh_size);
|
||||
}
|
||||
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (!stream->streaming) {
|
||||
rkispp_write(dev, RKISPP_FEC_WR_Y_BASE, hw->dummy_buf.dma_addr);
|
||||
rkispp_write(dev, RKISPP_FEC_WR_UV_BASE, hw->dummy_buf.dma_addr);
|
||||
}
|
||||
|
||||
if (vdev->monitor.is_en) {
|
||||
init_completion(&vdev->monitor.fec.cmpl);
|
||||
schedule_work(&vdev->monitor.fec.work);
|
||||
}
|
||||
rkispp_set_clk_rate(dev->hw_dev->clks[0], dev->hw_dev->core_clk_max);
|
||||
v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
|
||||
"%s size:%dx%d ctrl:0x%x core_ctrl:0x%x\n",
|
||||
__func__, in_width, in_height,
|
||||
rkispp_read(dev, RKISPP_FEC_CTRL),
|
||||
rkispp_read(dev, RKISPP_FEC_CORE_CTRL));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void fec_free_buf(struct rkispp_device *dev)
|
||||
{
|
||||
struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
|
||||
struct list_head *list = &vdev->fec.list_rd;
|
||||
struct rkisp_ispp_buf *dbufs;
|
||||
|
||||
if (vdev->fec.cur_rd)
|
||||
vdev->fec.cur_rd = NULL;
|
||||
while (!list_empty(list)) {
|
||||
dbufs = get_list_buf(list, true);
|
||||
if (dbufs->is_isp)
|
||||
v4l2_subdev_call(dev->ispp_sdev.remote_sd,
|
||||
video, s_rx_buffer, dbufs, NULL);
|
||||
else
|
||||
get_list_buf(list, false);
|
||||
}
|
||||
}
|
||||
|
||||
static int config_modules(struct rkispp_device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
|
||||
"stream module ens:0x%x\n", dev->stream_vdev.module_ens);
|
||||
dev->stream_vdev.monitor.monitoring_module = 0;
|
||||
dev->stream_vdev.monitor.restart_module = 0;
|
||||
dev->stream_vdev.monitor.is_restart = false;
|
||||
dev->stream_vdev.monitor.retry = 0;
|
||||
init_completion(&dev->stream_vdev.monitor.cmpl);
|
||||
|
||||
ret = config_fec(dev);
|
||||
if (ret < 0)
|
||||
goto free_fec;
|
||||
|
||||
/* config default params */
|
||||
dev->params_vdev.params_ops->rkispp_params_cfg(&dev->params_vdev, 0);
|
||||
|
||||
return 0;
|
||||
free_fec:
|
||||
fec_free_buf(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void fec_work_event(struct rkispp_device *dev,
|
||||
void *buff_rd,
|
||||
bool is_isr, bool is_quick)
|
||||
{
|
||||
struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
|
||||
struct rkispp_monitor *monitor = &vdev->monitor;
|
||||
struct list_head *list = &vdev->fec.list_rd;
|
||||
void __iomem *base = dev->hw_dev->base_addr;
|
||||
struct rkispp_stream *stream = &vdev->stream[STREAM_II];
|
||||
unsigned long lock_flags = 0, lock_flags1 = 0;
|
||||
bool is_start = false;
|
||||
struct rkisp_ispp_reg *reg_buf = NULL;
|
||||
struct rkispp_buffer *inbuf;
|
||||
struct v4l2_subdev *sd = NULL;
|
||||
u32 val;
|
||||
struct rkisp_ispp_buf *buf_rd = buff_rd;
|
||||
|
||||
if (!(vdev->module_ens & ISPP_MODULE_FEC))
|
||||
return;
|
||||
if (dev->inp == INP_ISP)
|
||||
sd = dev->ispp_sdev.remote_sd;
|
||||
spin_lock_irqsave(&vdev->fec.buf_lock, lock_flags);
|
||||
/* event from fec frame end */
|
||||
if (!buf_rd && is_isr) {
|
||||
vdev->fec.is_end = true;
|
||||
if (vdev->fec.cur_rd) {
|
||||
if (sd) {
|
||||
v4l2_subdev_call(sd, video, s_rx_buffer, vdev->fec.cur_rd, NULL);
|
||||
} else if (stream->streaming && vdev->fec.cur_rd->priv) {
|
||||
inbuf = vdev->fec.cur_rd->priv;
|
||||
vb2_buffer_done(&inbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
}
|
||||
vdev->fec.cur_rd = NULL;
|
||||
}
|
||||
}
|
||||
spin_lock_irqsave(&monitor->lock, lock_flags1);
|
||||
if (monitor->is_restart && buf_rd) {
|
||||
list_add_tail(&buf_rd->list, list);
|
||||
goto restart_unlock;
|
||||
}
|
||||
|
||||
if (buf_rd && vdev->fec.is_end && list_empty(list)) {
|
||||
/* fec read buf from nr */
|
||||
vdev->fec.cur_rd = buf_rd;
|
||||
} else if (vdev->fec.is_end && !list_empty(list)) {
|
||||
/* fec read buf from list
|
||||
* fec processing slow than nr
|
||||
* new read buf from nr into list
|
||||
*/
|
||||
vdev->fec.cur_rd = get_list_buf(list, true);
|
||||
if (buf_rd)
|
||||
list_add_tail(&buf_rd->list, list);
|
||||
} else if (!vdev->fec.is_end && buf_rd) {
|
||||
/* fec no idle
|
||||
* new read buf from nr into list
|
||||
*/
|
||||
list_add_tail(&buf_rd->list, list);
|
||||
}
|
||||
|
||||
if (vdev->fec.cur_rd && vdev->fec.is_end) {
|
||||
if (vdev->fec.cur_rd->priv) {
|
||||
inbuf = vdev->fec.cur_rd->priv;
|
||||
val = inbuf->buff_addr[RKISPP_PLANE_Y];
|
||||
rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
|
||||
val = inbuf->buff_addr[RKISPP_PLANE_UV];
|
||||
rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
|
||||
} else {
|
||||
struct rkispp_isp_buf_pool *buf;
|
||||
|
||||
buf = get_pool_buf(dev, vdev->fec.cur_rd);
|
||||
val = buf->dma[GROUP_BUF_PIC];
|
||||
rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
|
||||
val += vdev->fec.uv_offset;
|
||||
rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
|
||||
}
|
||||
is_start = true;
|
||||
}
|
||||
|
||||
if (is_start) {
|
||||
u32 seq = 0;
|
||||
u64 timestamp = 0;
|
||||
|
||||
if (vdev->fec.cur_rd) {
|
||||
seq = vdev->fec.cur_rd->frame_id;
|
||||
timestamp = vdev->fec.cur_rd->frame_timestamp;
|
||||
dev->ispp_sdev.frm_sync_seq = seq;
|
||||
dev->ispp_sdev.frame_timestamp = timestamp;
|
||||
rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x00, SW_FEC_EN);
|
||||
}
|
||||
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (stream->streaming && !stream->is_cfg)
|
||||
secure_config_mb(stream);
|
||||
|
||||
if (!dev->hw_dev->is_single)
|
||||
rkispp_update_regs(dev, RKISPP_CTRL, RKISPP_FEC_SRC_SIZE);
|
||||
writel(FEC_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
|
||||
|
||||
v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
|
||||
"FEC start seq:%d | Y_SHD rd:0x%x\n",
|
||||
seq, readl(base + RKISPP_FEC_RD_Y_BASE_SHD));
|
||||
v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
|
||||
"%s stream:%d Y:0x%x UV:0x%x\n",
|
||||
__func__, stream->id,
|
||||
rkispp_read(dev, stream->config->reg.cur_y_base),
|
||||
rkispp_read(dev, stream->config->reg.cur_uv_base));
|
||||
vdev->fec.dbg.id = seq;
|
||||
vdev->fec.dbg.timestamp = ktime_get_ns();
|
||||
if (monitor->is_en) {
|
||||
monitor->fec.time = vdev->fec.dbg.interval / 1000 / 1000;
|
||||
monitor->monitoring_module |= MONITOR_FEC;
|
||||
if (!completion_done(&monitor->fec.cmpl))
|
||||
complete(&monitor->fec.cmpl);
|
||||
}
|
||||
|
||||
if (stream->is_reg_withstream)
|
||||
rkispp_find_regbuf_by_id(dev, ®_buf, dev->dev_id, seq);
|
||||
|
||||
if (!dev->hw_dev->is_shutdown)
|
||||
writel(FEC_ST, base + RKISPP_CTRL_STRT);
|
||||
|
||||
vdev->fec.is_end = false;
|
||||
}
|
||||
restart_unlock:
|
||||
spin_unlock_irqrestore(&monitor->lock, lock_flags1);
|
||||
spin_unlock_irqrestore(&vdev->fec.buf_lock, lock_flags);
|
||||
|
||||
}
|
||||
|
||||
void rkispp_module_work_event(struct rkispp_device *dev,
|
||||
void *buf_rd, void *buf_wr,
|
||||
u32 module, bool is_isr)
|
||||
{
|
||||
|
||||
if (dev->hw_dev->is_shutdown)
|
||||
return;
|
||||
|
||||
if (dev->ispp_sdev.state != ISPP_STOP)
|
||||
fec_work_event(dev, buf_rd, is_isr, false);
|
||||
|
||||
/* cur frame (tnr->nr->fec) done for next frame
|
||||
* fec start at nr end if fec enable, and fec can async with
|
||||
* tnr different frames for single device.
|
||||
* tnr->nr->fec frame0
|
||||
* |->tnr->nr->fec frame1
|
||||
*/
|
||||
if (is_isr && !buf_rd && !buf_wr &&
|
||||
(module == ISPP_MODULE_FEC && dev->hw_dev->is_single)) {
|
||||
dev->stream_vdev.monitor.retry = 0;
|
||||
rkispp_event_handle(dev, CMD_QUEUE_DMABUF, NULL);
|
||||
|
||||
}
|
||||
|
||||
if (dev->ispp_sdev.state == ISPP_STOP) {
|
||||
if ((module & ISPP_MODULE_FEC) && buf_rd) {
|
||||
struct rkisp_ispp_buf *buf = buf_rd;
|
||||
|
||||
if (buf->is_isp)
|
||||
v4l2_subdev_call(dev->ispp_sdev.remote_sd,
|
||||
video, s_rx_buffer, buf, NULL);
|
||||
}
|
||||
if (!dev->hw_dev->is_idle)
|
||||
dev->hw_dev->is_idle = true;
|
||||
}
|
||||
}
|
||||
|
||||
static void rkispp_destroy_buf(struct rkispp_stream *stream)
|
||||
{
|
||||
struct rkispp_device *dev = stream->isppdev;
|
||||
struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
|
||||
|
||||
if (atomic_read(&vdev->refcnt) == 1) {
|
||||
vdev->irq_ends = 0;
|
||||
fec_free_buf(dev);
|
||||
rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static int start_isp(struct rkispp_device *dev)
|
||||
{
|
||||
struct rkispp_subdev *ispp_sdev = &dev->ispp_sdev;
|
||||
struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
|
||||
struct rkispp_stream *stream;
|
||||
struct rkisp_ispp_mode mode;
|
||||
int ret;
|
||||
|
||||
if (dev->inp != INP_ISP || ispp_sdev->state)
|
||||
return 0;
|
||||
|
||||
if (dev->stream_sync) {
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (stream->linked && !stream->streaming)
|
||||
return 0;
|
||||
} else if (atomic_read(&vdev->refcnt) > 1) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
rkispp_start_3a_run(dev);
|
||||
|
||||
mutex_lock(&dev->hw_dev->dev_lock);
|
||||
|
||||
mode.work_mode = ISP_ISPP_422;
|
||||
mode.buf_num = 1;
|
||||
mode.buf_num += RKISP_BUF_MAX + 2 * (dev->hw_dev->dev_num - 1);
|
||||
|
||||
ret = v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
|
||||
RKISP_ISPP_CMD_SET_MODE, &mode);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = config_modules(dev);
|
||||
if (ret) {
|
||||
rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
|
||||
mode.work_mode = ISP_ISPP_INIT_FAIL;
|
||||
v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
|
||||
RKISP_ISPP_CMD_SET_MODE, &mode);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (dev->hw_dev->is_single)
|
||||
writel(ALL_FORCE_UPD, dev->hw_dev->base_addr + RKISPP_CTRL_UPDATE);
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (stream->streaming)
|
||||
stream->is_upd = true;
|
||||
if (dev->isp_mode & ISP_ISPP_QUICK)
|
||||
rkispp_set_bits(dev, RKISPP_CTRL_QUICK, 0, GLB_QUICK_EN);
|
||||
|
||||
dev->isr_cnt = 0;
|
||||
dev->isr_err_cnt = 0;
|
||||
ret = v4l2_subdev_call(&ispp_sdev->sd, video, s_stream, true);
|
||||
err:
|
||||
mutex_unlock(&dev->hw_dev->dev_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void check_to_force_update(struct rkispp_device *dev, u32 mis_val)
|
||||
{
|
||||
struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
|
||||
struct rkispp_stream *stream;
|
||||
u32 mask = FEC_INT;
|
||||
|
||||
vdev->irq_ends |= (mis_val & mask);
|
||||
v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
|
||||
"irq_ends:0x%x mask:0x%x\n",
|
||||
vdev->irq_ends, mask);
|
||||
if (vdev->irq_ends != mask)
|
||||
return;
|
||||
vdev->irq_ends = 0;
|
||||
if (mis_val & FEC_INT)
|
||||
rkispp_module_work_event(dev, NULL, NULL,
|
||||
ISPP_MODULE_FEC, true);
|
||||
|
||||
stream = &vdev->stream[STREAM_MB];
|
||||
if (stream->streaming)
|
||||
stream->is_upd = true;
|
||||
|
||||
}
|
||||
|
||||
static struct rkispp_stream_ops rkispp_stream_ops = {
|
||||
.config_modules = config_modules,
|
||||
.destroy_buf = rkispp_destroy_buf,
|
||||
.fec_work_event = fec_work_event,
|
||||
.start_isp = start_isp,
|
||||
.check_to_force_update = check_to_force_update,
|
||||
.update_mi = update_mi,
|
||||
.rkispp_module_work_event = rkispp_module_work_event,
|
||||
};
|
||||
|
||||
void rkispp_stream_init_ops_v20(struct rkispp_stream_vdev *stream_vdev)
|
||||
{
|
||||
stream_vdev->stream_ops = &rkispp_stream_ops;
|
||||
}
|
||||
33
include/uapi/linux/fec-config.h
Normal file
33
include/uapi/linux/fec-config.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT)
|
||||
*
|
||||
* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_FEC_CONFIG_H
|
||||
#define _UAPI_FEC_CONFIG_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/v4l2-controls.h>
|
||||
|
||||
#define FEC_API_VERSION KERNEL_VERSION(1, 0, 0)
|
||||
struct fec_config {
|
||||
u32 mesh_density;
|
||||
u32 src_width;
|
||||
u32 src_height;
|
||||
u32 dst_width;
|
||||
u32 dst_height;
|
||||
u32 mesh_size;
|
||||
s32 buf_fd;
|
||||
u32 fec_bic_mode;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct fec_params_cfg {
|
||||
u32 module_en_update;
|
||||
u32 module_ens;
|
||||
u32 module_cfg_update;
|
||||
|
||||
u32 frame_id;
|
||||
struct fec_config fec_cfg;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user