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vdin: add reset patch && viu debug interface

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PD#156734: vdin: add reset patch && viu debug interface

1.add vdin reset for g12a
2.add viu-vd1/vd2/osd1/osd2 loop debug interface
3.add hiu reg r/w support
4.delete sr temp debug code

Change-Id: Ia503b2471827f835394dd81667a4672cb0434e69
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>
This commit is contained in:
Dezhi Kong
2018-02-06 14:55:11 +08:00
committed by Yixun Lan
parent 9ea633e1ec
commit 01f9406725
6 changed files with 134 additions and 20 deletions
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3
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -4387,7 +4387,8 @@ static int __init aml_vecm_init(void)
pr_info("%s:module init\n", __func__);
/* remap the hiu bus */
if (is_meson_txlx_cpu() || is_meson_txhd_cpu())
if (is_meson_txlx_cpu() || is_meson_txhd_cpu() ||
is_meson_g12a_cpu())
hiu_reg_base = 0xff63c000;
else
hiu_reg_base = 0xc883c000;

2
drivers/amlogic/media/video_sink/vpp.c
View File

@@ -1584,8 +1584,6 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
int tmp_data2 = 0;
unsigned int data_path_chose;
if (super_scaler == 0)
return 0;
/* top config */
tmp_data = VSYNC_RD_MPEG_REG(VPP_SRSHARP0_CTRL);
if (sr0_sr1_refresh) {

36
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
View File

@@ -139,7 +139,8 @@ static unsigned int vpu_reg_27af = 0x3;
#define MEAS_MUX_DTV 6
#define MEAS_MUX_ISP 8
#define MEAS_MUX_656_B 9
#define MEAS_MUX_VIU 6
#define MEAS_MUX_VIU1 6
#define MEAS_MUX_VIU2 9
#define HDMI_DE_REPEAT_DONE_FLAG 0xF0
#define DECIMATION_REAL_RANGE 0x0F
@@ -574,7 +575,8 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
if ((is_meson_gxbb_cpu() || is_meson_gxtvbb_cpu()) &&
(bt_path == BT_PATH_GPIO_B))
meas_mux = MEAS_MUX_656_B;
else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu()) &&
else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu() ||
is_meson_g12a_cpu()) &&
(bt_path == BT_PATH_GPIO))
meas_mux = MEAS_MUX_656;
else
@@ -598,8 +600,11 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
case 0x80: /* dvin */
meas_mux = MEAS_MUX_DVIN;
break;
case 0xa0:/* viu */
meas_mux = MEAS_MUX_VIU1;
break;
case 0xc0:/* viu */
meas_mux = MEAS_MUX_VIU;
meas_mux = MEAS_MUX_VIU2;
break;
case 0x100:/* dtv mipi */
meas_mux = MEAS_MUX_DTV;
@@ -651,7 +656,7 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
/*attention:new add for bt656
*0x02: /bt656/
a.BT_PATH_GPIO: gxl & gxm
a.BT_PATH_GPIO: gxl & gxm & g12a
b.BT_PATH_GPIO_B:gxtvbb & gxbb
c.txl and txlx don't support bt656
*/
@@ -681,7 +686,8 @@ void vdin_set_top(unsigned int offset,
vdin_mux = VDIN_MUX_656_B;
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
VDI9_ASFIFO_CTRL_BIT, VDI9_ASFIFO_CTRL_WID);
} else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu()) &&
} else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu() ||
is_meson_g12a_cpu()) &&
(bt_path == BT_PATH_GPIO)) {
vdin_mux = VDIN_MUX_656;
wr_bits(offset, VDIN_ASFIFO_CTRL0, 0xe4,
@@ -727,7 +733,7 @@ void vdin_set_top(unsigned int offset,
break;
case 0xa0:/*viu1*/
vdin_mux = VDIN_MUX_VIU_1;
if (port == TVIN_PORT_VIU1_VIDEO)
if (port != TVIN_PORT_VIU1)
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
VDI6_ASFIFO_CTRL_BIT, VDI6_ASFIFO_CTRL_WID);
else
@@ -736,7 +742,7 @@ void vdin_set_top(unsigned int offset,
break;
case 0xc0: /* viu2 */
vdin_mux = VDIN_MUX_VIU_2;
if (port == TVIN_PORT_VIU1_VIDEO)
if (port != TVIN_PORT_VIU2)
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
VDI8_ASFIFO_CTRL_BIT, VDI8_ASFIFO_CTRL_WID);
else
@@ -1442,6 +1448,10 @@ static void vdin_set_color_matrix0_g12a(unsigned int offset,
wr_bits(offset, VDIN_HDR2_MATRIXI_EN_CTRL, 1, 0, 1);
wr_bits(offset, VDIN_HDR2_CTRL, 1, 16, 1);
wr_bits(offset, VDIN_HDR2_CTRL, 0, 13, 1);
wr_bits(offset, VDIN_MATRIX_CTRL, 0,
VDIN_MATRIX0_BYPASS_BIT, VDIN_MATRIX0_BYPASS_WID);
wr_bits(offset, VDIN_MATRIX_CTRL, 1,
VDIN_MATRIX_EN_BIT, VDIN_MATRIX_EN_WID);
}
}
@@ -1995,11 +2005,19 @@ void vdin_set_canvas_id(struct vdin_dev_s *devp, unsigned int rdma_enable,
unsigned int canvas_id)
{
#ifdef CONFIG_AML_RDMA
if (rdma_enable)
if (rdma_enable) {
if (is_meson_g12a_cpu()) {
rdma_write_reg_bits(devp->rdma_handle,
VDIN_COM_CTRL0+devp->addr_offset, 1,
VDIN_FORCEGOLINE_EN_BIT, 1);
rdma_write_reg_bits(devp->rdma_handle,
VDIN_COM_CTRL0+devp->addr_offset, 0,
VDIN_FORCEGOLINE_EN_BIT, 1);
}
rdma_write_reg_bits(devp->rdma_handle,
VDIN_WR_CTRL+devp->addr_offset,
canvas_id, WR_CANVAS_BIT, WR_CANVAS_WID);
else
} else
#endif
wr_bits(devp->addr_offset, VDIN_WR_CTRL, canvas_id,
WR_CANVAS_BIT, WR_CANVAS_WID);

74
drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c
View File

@@ -144,6 +144,10 @@ static ssize_t vdin_attr_show(struct device *dev,
"/sys/class/vdin/vdinx/attr.\n");
len += sprintf(buf+len,
"echo v4l2start bt656/viuin/video/isp h_actve v_active");
len += sprintf(buf+len,
"viuin/viu_wb0_vd1/viu_wb0_vd1/viu_wb0_post_blend/viu_wb0_osd1/viu_wb0_osd2");
len += sprintf(buf+len,
"viuin2/viu2_wb0_vd1/viu2_wb0_vd1/viu2_wb0_post_blend/viu2_wb0_osd1/viu2_wb0_osd2");
len += sprintf(buf+len,
"frame_rate cfmt dfmt scan_fmt > /sys/class/vdin/vdinx/attr.\n");
len += sprintf(buf+len,
@@ -971,10 +975,76 @@ start_chk:
pr_info(" port is TVIN_PORT_CAMERA\n");
} else if (!strcmp(parm[1], "viuin")) {
param.port = TVIN_PORT_VIU1;
pr_info(" port is TVIN_PORT_VIU1\n");
pr_info(" port is TVIN_PORT_VIU\n");
} else if (!strcmp(parm[1], "video")) {
param.port = TVIN_PORT_VIU1_VIDEO;
pr_info(" port is TVIN_PORT_VIU1_VIDEO\n");
pr_info(" port is TVIN_PORT_VIU_VIDEO\n");
} else if (!strcmp(parm[1], "viu_wb0_vd1")) {
param.port = TVIN_PORT_VIU1_WB0_VD1;
pr_info(" port is TVIN_PORT_VIU_WB0_VD1\n");
} else if (!strcmp(parm[1], "viu_wb0_vd2")) {
param.port = TVIN_PORT_VIU1_WB0_VD2;
pr_info(" port is TVIN_PORT_VIU_WB0_VD2\n");
} else if (!strcmp(parm[1], "viu_wb0_osd1")) {
param.port = TVIN_PORT_VIU1_WB0_OSD1;
pr_info(" port is TVIN_PORT_VIU_WB0_OSD1\n");
} else if (!strcmp(parm[1], "viu_wb0_osd2")) {
param.port = TVIN_PORT_VIU1_WB0_OSD2;
pr_info(" port is TVIN_PORT_VIU_WB0_OSD2\n");
} else if (!strcmp(parm[1], "viu_wb0_post_blend")) {
param.port = TVIN_PORT_VIU1_WB0_POST_BLEND;
pr_info(" port is TVIN_PORT_VIU_WB0_POST_BLEND\n");
} else if (!strcmp(parm[1], "viu_wb1_vd1")) {
param.port = TVIN_PORT_VIU1_WB1_VD1;
pr_info(" port is TVIN_PORT_VIU_WB1_VD1\n");
} else if (!strcmp(parm[1], "viu_wb1_vd2")) {
param.port = TVIN_PORT_VIU1_WB1_VD2;
pr_info(" port is TVIN_PORT_VIU_WB1_VD2\n");
} else if (!strcmp(parm[1], "viu_wb1_osd1")) {
param.port = TVIN_PORT_VIU1_WB1_OSD1;
pr_info(" port is TVIN_PORT_VIU_WB1_OSD1\n");
} else if (!strcmp(parm[1], "viu_wb0_osd2")) {
param.port = TVIN_PORT_VIU1_WB1_OSD2;
pr_info(" port is TVIN_PORT_VIU_WB1_OSD2\n");
} else if (!strcmp(parm[1], "viu_wb1_post_blend")) {
param.port = TVIN_PORT_VIU1_WB1_POST_BLEND;
pr_info(" port is TVIN_PORT_VIU_WB1_POST_BLEND\n");
} else if (!strcmp(parm[1], "viuin2")) {
param.port = TVIN_PORT_VIU2;
pr_info(" port is TVIN_PORT_VIU\n");
} else if (!strcmp(parm[1], "video2")) {
param.port = TVIN_PORT_VIU2_VIDEO;
pr_info(" port is TVIN_PORT_VIU_VIDEO\n");
} else if (!strcmp(parm[1], "viu2_wb0_vd1")) {
param.port = TVIN_PORT_VIU2_WB0_VD1;
pr_info(" port is TVIN_PORT_VIU_WB0_VD1\n");
} else if (!strcmp(parm[1], "viu2_wb0_vd2")) {
param.port = TVIN_PORT_VIU2_WB0_VD2;
pr_info(" port is TVIN_PORT_VIU_WB0_VD2\n");
} else if (!strcmp(parm[1], "viu2_wb0_osd1")) {
param.port = TVIN_PORT_VIU2_WB0_OSD1;
pr_info(" port is TVIN_PORT_VIU_WB0_OSD1\n");
} else if (!strcmp(parm[1], "viu2_wb0_osd2")) {
param.port = TVIN_PORT_VIU2_WB0_OSD2;
pr_info(" port is TVIN_PORT_VIU_WB0_OSD2\n");
} else if (!strcmp(parm[1], "viu2_wb0_post_blend")) {
param.port = TVIN_PORT_VIU2_WB0_POST_BLEND;
pr_info(" port is TVIN_PORT_VIU_WB0_POST_BLEND\n");
} else if (!strcmp(parm[1], "viu2_wb1_vd1")) {
param.port = TVIN_PORT_VIU2_WB1_VD1;
pr_info(" port is TVIN_PORT_VIU_WB1_VD1\n");
} else if (!strcmp(parm[1], "viu2_wb1_vd2")) {
param.port = TVIN_PORT_VIU2_WB1_VD2;
pr_info(" port is TVIN_PORT_VIU_WB1_VD2\n");
} else if (!strcmp(parm[1], "viu2_wb1_osd1")) {
param.port = TVIN_PORT_VIU2_WB1_OSD1;
pr_info(" port is TVIN_PORT_VIU_WB1_OSD1\n");
} else if (!strcmp(parm[1], "viu2_wb0_osd2")) {
param.port = TVIN_PORT_VIU2_WB1_OSD2;
pr_info(" port is TVIN_PORT_VIU_WB1_OSD2\n");
} else if (!strcmp(parm[1], "viu2_wb1_post_blend")) {
param.port = TVIN_PORT_VIU2_WB1_POST_BLEND;
pr_info(" port is TVIN_PORT_VIU_WB1_POST_BLEND\n");
} else if (!strcmp(parm[1], "isp")) {
param.port = TVIN_PORT_ISP;
pr_info(" port is TVIN_PORT_ISP\n");

1
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -423,6 +423,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
/*gxbb/gxl/gxm use clkb as vdin clk,
*for clkb is low speed,wich is enough for 1080p process,
*gxtvbb/txl use vpu clk for process 4k
*g12a use vpu clk for process 4K input buf can't output 4k
*/
if (is_meson_gxl_cpu() || is_meson_gxm_cpu() || is_meson_gxbb_cpu() ||
is_meson_txhd_cpu())

38
drivers/amlogic/media/vin/tvin/viu/viuin.c
View File

@@ -61,6 +61,10 @@
#define VPU_VIU2VDIN1_HDN_CTRL 0x2784
#define VPU_VENCX_CLK_CTRL 0x2785
#define VPP_WRBAK_CTRL 0x1df9
#define VPU_422TO444_CTRL0 0x274b
#define VPU_422TO444_CTRL1 0x274c
#define VPU_422TO444_CTRL2 0x274d
#define WR_BACK_MISC_CTRL 0x1a0d
static unsigned int vsync_enter_line_curr;
@@ -139,7 +143,8 @@ static inline uint32_t rd_bits_viu(uint32_t reg,
static int viuin_support(struct tvin_frontend_s *fe, enum tvin_port_e port)
{
if (port == TVIN_PORT_VIU1 || port == TVIN_PORT_VIU1_VIDEO)
if ((port >= TVIN_PORT_VIU1) &&
(port <= TVIN_PORT_VIU2_WB1_POST_BLEND))
return 0;
else
return -1;
@@ -201,7 +206,8 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
if (devp->parm.v_active == 2160 && devp->parm.frame_rate > 30)
/* 1/2 down scaling */
wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
}
} else
wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
if (is_meson_g12a_cpu()) {
if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
(port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
@@ -218,10 +224,14 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
else if (port >> 8 == 0xc0)
viu_sel = 2;
if (viu_sel == 1) {
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0, 0, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 0, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0, 8, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 8, 5);
} else if (viu_sel == 2) {
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0, 16, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 16, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0, 24, 5);
wr_bits_viu(VPU_VIU_VDIN_IF_MUX_CTRL, viu_mux, 24, 5);
} else {
wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0);
@@ -260,6 +270,21 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
wr_bits_viu(VPP_WRBAK_CTRL, 5, 4, 3);
else
wr_bits_viu(VPP_WRBAK_CTRL, 0, 4, 3);
/*wrback hsync en*/
if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
(port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
((port >= TVIN_PORT_VIU2_WB0_VD1) &&
(port <= TVIN_PORT_VIU2_WB0_POST_BLEND))) {
wr_bits_viu(WR_BACK_MISC_CTRL, 1, 0, 1);
wr_bits_viu(WR_BACK_MISC_CTRL, 0, 1, 1);
} else if (((port >= TVIN_PORT_VIU1_WB1_VD1) &&
(port <= TVIN_PORT_VIU1_WB1_POST_BLEND)) ||
((port >= TVIN_PORT_VIU2_WB1_VD1) &&
(port <= TVIN_PORT_VIU2_WB1_POST_BLEND))) {
wr_bits_viu(WR_BACK_MISC_CTRL, 0, 0, 1);
wr_bits_viu(WR_BACK_MISC_CTRL, 1, 1, 1);
} else
wr_bits_viu(WR_BACK_MISC_CTRL, 0, 0, 2);
} else {
wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 4, 4);
wr_bits_viu(VPU_VIU_VENC_MUX_CTRL, viu_mux, 8, 4);
@@ -272,8 +297,7 @@ static void viuin_close(struct tvin_frontend_s *fe)
{
struct viuin_s *devp = container_of(fe, struct viuin_s, frontend);
if (0)/*temp mark for pxp verify*/
viuin_check_venc_line(devp);
viuin_check_venc_line(devp);
memset(&devp->parm, 0, sizeof(struct vdin_parm_s));
/*close the venc to vdin path*/
if (open_cnt)
@@ -356,10 +380,12 @@ static void viuin_sig_property(struct tvin_frontend_s *fe,
if (devp->parm.port == TVIN_PORT_VIU1_VIDEO)
prop->color_format = TVIN_YUV444;
else {
else if ((devp->parm.port == TVIN_PORT_VIU1) ||
(devp->parm.port == TVIN_PORT_VIU2)) {
vinfo = get_current_vinfo();
prop->color_format = vinfo->viu_color_fmt;
}
} else
prop->color_format = devp->parm.cfmt;
prop->dest_cfmt = devp->parm.dfmt;
prop->scaling4w = devp->parm.dest_hactive;