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pinctrl: rockchip: add support for rk1808 SoCs

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Add support for pinctrl on RK1808 SoCs.

Change-Id: I0688a61af139cc24363b7515036c80d25ff6a738
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
2021-04-02 11:49:46 +08:00
parent 659709bf6a
commit 026f6903b1
1 changed files with 230 additions and 0 deletions
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230
drivers/pinctrl/pinctrl-rockchip.c
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@@ -91,6 +91,7 @@ static const struct rockchip_gpio_regs gpio_regs_v2 = {
enum rockchip_pinctrl_type {
PX30,
RV1108,
RK1808,
RK2928,
RK3066B,
RK3128,
@@ -952,6 +953,87 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
*bit = data->bit;
}
static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
{
/* i2c2m0_sda */
.bank_num = 3,
.pin = 12,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 3),
}, {
/* i2c2m1_sda */
.bank_num = 1,
.pin = 13,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 3) | BIT(3),
}, {
/* spi2m0_miso */
.bank_num = 1,
.pin = 6,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 4),
}, {
/* spi2m1_miso */
.bank_num = 2,
.pin = 4,
.func = 3,
.route_offset = 0x190,
.route_val = BIT(16 + 4) | BIT(4),
}, {
/* spi1m0_miso */
.bank_num = 4,
.pin = 15,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 5),
}, {
/* spi1m1_miso */
.bank_num = 3,
.pin = 26,
.func = 3,
.route_offset = 0x190,
.route_val = BIT(16 + 5) | BIT(5),
}, {
/* uart1_rxm0 */
.bank_num = 4,
.pin = 8,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 13),
}, {
/* uart1_rxm1 */
.bank_num = 1,
.pin = 12,
.func = 3,
.route_offset = 0x190,
.route_val = BIT(16 + 13) | BIT(13),
}, {
/* uart2_rxm0 */
.bank_num = 4,
.pin = 3,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 14) | BIT(16 + 15),
}, {
/* uart2_rxm1 */
.bank_num = 2,
.pin = 25,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(14),
}, {
/* uart2_rxm2 */
.bank_num = 3,
.pin = 4,
.func = 2,
.route_offset = 0x190,
.route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15),
},
};
static struct rockchip_mux_route_data px30_mux_route_data[] = {
{
/* cif-d2m0 */
@@ -2028,6 +2110,111 @@ static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK1808_PULL_PMU_OFFSET 0x10
#define RK1808_PULL_GRF_OFFSET 0x80
#define RK1808_PULL_PINS_PER_REG 8
#define RK1808_PULL_BITS_PER_PIN 2
#define RK1808_PULL_BANK_STRIDE 16
static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK1808_PULL_PMU_OFFSET;
} else {
*reg = RK1808_PULL_GRF_OFFSET;
*regmap = info->regmap_base;
*reg += (bank->bank_num - 1) * RK1808_PULL_BANK_STRIDE;
}
*reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
*bit *= RK1808_PULL_BITS_PER_PIN;
}
#define RK1808_DRV_PMU_OFFSET 0x20
#define RK1808_DRV_GRF_OFFSET 0x140
#define RK1808_DRV_BITS_PER_PIN 2
#define RK1808_DRV_PINS_PER_REG 8
#define RK1808_DRV_BANK_STRIDE 16
static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK1808_DRV_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RK1808_DRV_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK1808_DRV_BANK_STRIDE;
}
*reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK1808_DRV_PINS_PER_REG;
*bit *= RK1808_DRV_BITS_PER_PIN;
}
#define RK1808_SR_PMU_OFFSET 0x0030
#define RK1808_SR_GRF_OFFSET 0x00c0
#define RK1808_SR_BANK_STRIDE 16
#define RK1808_SR_PINS_PER_REG 8
static int rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK1808_SR_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RK1808_SR_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK1808_SR_BANK_STRIDE;
}
*reg += ((pin_num / RK1808_SR_PINS_PER_REG) * 4);
*bit = pin_num % RK1808_SR_PINS_PER_REG;
return 0;
}
#define RK1808_SCHMITT_PMU_OFFSET 0x0040
#define RK1808_SCHMITT_GRF_OFFSET 0x0100
#define RK1808_SCHMITT_BANK_STRIDE 16
#define RK1808_SCHMITT_PINS_PER_REG 8
static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RK1808_SCHMITT_PMU_OFFSET;
} else {
*regmap = info->regmap_base;
*reg = RK1808_SCHMITT_GRF_OFFSET;
*reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
*bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
return 0;
}
#define RK2928_PULL_OFFSET 0x118
#define RK2928_PULL_PINS_PER_REG 16
#define RK2928_PULL_BANK_STRIDE 8
@@ -2665,6 +2852,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
: PIN_CONFIG_BIAS_DISABLE;
case PX30:
case RV1108:
case RK1808:
case RK3188:
case RK3288:
case RK3308:
@@ -2710,6 +2898,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
case RK1808:
case RK3188:
case RK3288:
case RK3308:
@@ -3102,6 +3291,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
case RK1808:
case RK3188:
case RK3288:
case RK3308:
@@ -4455,6 +4645,44 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk1808_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT),
};
static struct rockchip_pin_ctrl rk1808_pin_ctrl = {
.pin_banks = rk1808_pin_banks,
.nr_banks = ARRAY_SIZE(rk1808_pin_banks),
.label = "RK1808-GPIO",
.type = RK1808,
.iomux_routes = rk1808_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
.grf_mux_offset = 0x0,
.pmu_mux_offset = 0x0,
.pull_calc_reg = rk1808_calc_pull_reg_and_bit,
.drv_calc_reg = rk1808_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
.slew_rate_calc_reg = rk1808_calc_slew_rate_reg_and_bit,
};
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -4823,6 +5051,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rk1808-pinctrl",
.data = &rk1808_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",