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rk3036:clk:rename clk_core_pre to clk_core

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张晴
2014-07-09 16:50:25 +08:00
parent 66d0558fda
commit 032de7a4eb
4 changed files with 23 additions and 28 deletions
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20
arch/arm/boot/dts/rk3036-clocks.dtsi
View File

@@ -138,7 +138,7 @@
status-reg = <0x0014 10>;
clocks = <&xin24m>;
clock-output-names = "clk_dpll";
rockchip,pll-type = <CLK_PLL_3188PLUS>;
rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
#clock-cells = <0>;
};
@@ -169,11 +169,11 @@
#address-cells = <1>;
#size-cells = <1>;
clk_core_pre_div: clk_core_pre_div {
clk_core_div: clk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_core_pre>;
clock-output-names = "clk_core_pre";
clocks = <&clk_core>;
clock-output-names = "clk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
@@ -183,11 +183,11 @@
/* reg[6:5]: reserved */
clk_core_pre: clk_core_pre_mux {
clk_core: clk_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_apll>, <&clk_gates0 6>;
clock-output-names = "clk_core_pre";
clock-output-names = "clk_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
@@ -226,7 +226,7 @@
pclk_dbg_div: pclk_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 4>;
clocks = <&clk_core_pre>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
@@ -236,7 +236,7 @@
aclk_core_pre: aclk_core_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core_pre>;
clocks = <&clk_core>;
clock-output-names = "aclk_core_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
@@ -1139,11 +1139,11 @@
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d0 0x4>;
clocks =
<&clk_core_pre>, <&clk_gpll>,
<&clk_core>, <&clk_gpll>,
<&clk_dpll>, <&aclk_cpu_pre>,
<&aclk_cpu_pre>, <&aclk_cpu_pre>,
<&clk_gpll>, <&clk_core_pre>,
<&clk_gpll>, <&clk_core>,
<&clk_gpll>, <&clk_i2s_pll>,
<&i2s_frac>, <&hclk_vio_pre>,

4
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -185,13 +185,13 @@
clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&clk_core_pre &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
<&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
<&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
<&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
<&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
<&clk_mac_pll &clk_apll>;
rockchip,clocks-init-rate =
<&clk_core_pre 816000000>, <&clk_gpll 594000000>,
<&clk_core 816000000>, <&clk_gpll 594000000>,
<&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
<&pclk_cpu_pre 75000000>, <&aclk_peri_pre 150000000>,
<&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,

16
drivers/clk/rockchip/clk-pll.h
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@@ -258,22 +258,6 @@
}
/***************************RK3036 PLL**************************************/
#define LPJ_24M (CLK_LOOPS_JIFFY_REF * 24) / CLK_LOOPS_RATE_REF
/*****cru reg offset*****/
#define RK3036_CRU_CLKSEL_CON 0x44
#define RK3036_CRU_CLKGATE_CON 0xd0
#define RK3036_CRU_GLB_SRST_FST 0x100
#define RK3036_CRU_GLB_SRST_SND 0x104
#define RK3036_CRU_SOFTRST_CON 0x110
#define RK3036_CRU_CLKSELS_CON_CNT (35)
#define RK3036_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
#define RK3036_CRU_CLKGATES_CON_CNT (10)
#define RK3036_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
#define RK3036_CRU_SOFTRSTS_CON_CNT (9)
#define RK3036_CRU_SOFTRSTS_CON(i) (RK3036_CRU_SOFTRST_CON + ((i) * 4))
/*PLL_CON 0,1,2*/
#define RK3036_PLL_PWR_ON (0)
#define RK3036_PLL_PWR_DN (1)

11
include/linux/rockchip/cru.h
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@@ -149,5 +149,16 @@ static inline void rk3288_cru_set_soft_reset(u32 idx, bool on)
#define RK3036_CRU_RST_ST 0x00160
#define RK3036_CRU_PLL_MASK_CON 0x001f0
#define RK3036_CRU_CLKSEL_CON 0x44
#define RK3036_CRU_CLKGATE_CON 0xd0
#define RK3036_CRU_CLKSELS_CON_CNT (35)
#define RK3036_CRU_CLKSELS_CON(i) (RK3036_CRU_CLKSEL_CON + ((i) * 4))
#define RK3036_CRU_CLKGATES_CON_CNT (10)
#define RK3036_CRU_CLKGATES_CON(i) (RK3036_CRU_CLKGATE_CON + ((i) * 4))
#define RK3036_CRU_SOFTRSTS_CON_CNT (9)
#define RK3036_CRU_SOFTRSTS_CON(i) (RK3036_CRU_SOFTRST_CON + ((i) * 4))
#endif