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drm/rockchip: vop2: No need to check act_width on rk3588

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VOP has a limitation of act_width on rk3568:

(1) The act_width should align as 4 pixel at afbc mode
(2) can't handle a act_width % 16 = 1

VOP on rk3588 has no such limitation.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I56f2ff32ac384bff81b6b911cd10ef599e5f44c3
This commit is contained in:
Andy Yan
2021-11-09 09:28:38 +08:00
committed by Tao Huang
parent fd1e752b58
commit 03b6bb941d
1 changed files with 16 additions and 11 deletions
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27
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -3638,20 +3638,25 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
}
/*
* This is workaround solution for IC design:
* esmart can't support scale down when actual_w % 16 == 1.
* Workaround only for rk3568 vop
*/
if (!(win->feature & WIN_FEATURE_AFBDC)) {
if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
actual_w -= 1;
if (vop2->version == VOP_VERSION_RK3568) {
/*
* This is workaround solution for IC design:
* esmart can't support scale down when actual_w % 16 == 1.
*/
if (!(win->feature & WIN_FEATURE_AFBDC)) {
if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
actual_w -= 1;
}
}
}
if (vpstate->afbc_en && actual_w % 4) {
DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
vp->id, win->name, actual_w);
actual_w = ALIGN_DOWN(actual_w, 4);
if (vpstate->afbc_en && actual_w % 4) {
DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
vp->id, win->name, actual_w);
actual_w = ALIGN_DOWN(actual_w, 4);
}
}
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);