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clk: rockchip: add clock ids for vip of RK3368 SoCs
Change-Id: I73ac0fd0010d0dc95c6da0770f85d7b35a11a628 Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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@@ -480,10 +480,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
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RK3368_CLKGATE_CON(4), 12, GFLAGS),
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COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
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COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
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RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
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RK3368_CLKGATE_CON(4), 5, GFLAGS),
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COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
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COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
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RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
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COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
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@@ -83,6 +83,8 @@
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#define SCLK_MACREF_OUT 128
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#define SCLK_MIPIDSI_24M 129
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#define SCLK_CRYPTO 130
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#define SCLK_VIP_SRC 131
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#define SCLK_VIP_OUT 132
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#define SCLK_TIMER10 133
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#define SCLK_TIMER11 134
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#define SCLK_TIMER12 135
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