clk: rockchip: add clock ids for vip of RK3368 SoCs

Change-Id: I73ac0fd0010d0dc95c6da0770f85d7b35a11a628
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Xu Jianqun
2016-02-03 16:48:25 +08:00
committed by Elaine Zhang
parent 00c75f4839
commit 03d96331f1
2 changed files with 4 additions and 2 deletions

View File

@@ -480,10 +480,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3368_CLKGATE_CON(4), 12, GFLAGS),
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(4), 5, GFLAGS),
COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,

View File

@@ -83,6 +83,8 @@
#define SCLK_MACREF_OUT 128
#define SCLK_MIPIDSI_24M 129
#define SCLK_CRYPTO 130
#define SCLK_VIP_SRC 131
#define SCLK_VIP_OUT 132
#define SCLK_TIMER10 133
#define SCLK_TIMER11 134
#define SCLK_TIMER12 135