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nand: add a new nand flash "TC58NVG2S0HBAI6" for SU customer
PD#149218: nand: add a new nand flash "TC58NVG2S0HBAI6" for SU customer Change-Id: I06b832365db629bd4c46fa6b6fa6ab4656267602 Signed-off-by: Yi Zeng <“yi.zeng@amlogic.com”>
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@@ -430,14 +430,9 @@ static inline void amlnf_clr_reg32_mask(uint32_t *_reg,
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#define NAND_ECC_NONE (0x0)
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#define NAND_ECC_BCH8 (0x1)
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#define NAND_ECC_BCH8_1K (0x2)
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#define NAND_ECC_BCH16_1K (0x3)
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#define NAND_ECC_BCH24_1K (0x4)
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#define NAND_ECC_BCH24_1K_M8 (0x3)
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#define NAND_ECC_BCH30_1K (0x5)
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#define NAND_ECC_BCH30_1K_M8 (0x4)
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#define NAND_ECC_BCH40_1K (0x6)
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#define NAND_ECC_BCH40_1K_M8 (0x5)
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#define NAND_ECC_BCH50_1K_M8 (0x6)
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#define NAND_ECC_BCH24_1K (0x3)
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#define NAND_ECC_BCH30_1K (0x4)
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#define NAND_ECC_BCH40_1K (0x5)
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/*NAND_ECC_BCH50_1K only for mtd for general*/
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#define NAND_ECC_BCH50_1K (0x6)
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#define NAND_ECC_BCH60_1K (0x7)
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@@ -455,17 +455,6 @@ static int m3_nand_options_confirm(struct aml_nand_chip *aml_chip)
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aml_chip->ecc_max = 8;
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chip->ecc.steps = mtd->writesize / chip->ecc.size;
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break;
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/*don't support for new chip(greater than m8)*/
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case NAND_ECC_BCH16_1K_MODE:
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chip->ecc.strength = 16;
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chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
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chip->ecc.bytes = NAND_BCH16_1K_ECC_SIZE;
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aml_chip->bch_mode = NAND_ECC_BCH16_1K;
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aml_chip->user_byte_mode = 2;
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aml_chip->ecc_cnt_limit = 14;
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aml_chip->ecc_max = 16;
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chip->ecc.steps = mtd->writesize / chip->ecc.size;
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break;
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case NAND_ECC_BCH24_1K_MODE:
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chip->ecc.strength = 24;
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@@ -314,6 +314,19 @@ struct aml_nand_flash_dev aml_nand_flash_ids[] = {
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0,
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(NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
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{"A revision NAND 512MB TC58NVG2S0HBAI6 ",
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{NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0x76},
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4096,
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512,
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0x40000,
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256,
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1,
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20,
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25,
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0,
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0,
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(NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
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{"A revision NAND 2Gib MT29F2G08-A",
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{NAND_MFR_MICRON, 0xda, 0x90, 0x95, 0x06},
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2048,
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@@ -4633,6 +4633,7 @@ int nand_scan_tail(struct mtd_info *mtd)
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break;
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case 64:
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case 128:
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case 256:
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mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
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break;
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default:
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