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drm/i915: Move dbuf details to INTEL_INFO->display

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DBUF is a display thing, so move it into the display
portion of the device info.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
2022-06-23 16:08:52 +03:00
parent 3cdcdc34f3
commit 04155815db
5 changed files with 20 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/display/intel_display.h
View File

@@ -193,7 +193,7 @@ enum plane_id {
#define for_each_dbuf_slice(__dev_priv, __slice) \
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
for_each_dbuf_slice((__dev_priv), (__slice)) \

2
drivers/gpu/drm/i915/display/intel_display_power.c
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@@ -1038,7 +1038,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
enum dbuf_slice slice;
drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,

18
drivers/gpu/drm/i915/i915_pci.c
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@@ -649,8 +649,8 @@ static const struct intel_device_info chv_info = {
.display.has_ipc = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.slice_mask = BIT(DBUF_S1)
.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.display.dbuf.slice_mask = BIT(DBUF_S1)
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -685,7 +685,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
.dbuf.slice_mask = BIT(DBUF_S1), \
.display.dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -722,14 +722,14 @@ static const struct intel_device_info skl_gt4_info = {
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.display.ver = 10,
.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
};
@@ -819,8 +819,8 @@ static const struct intel_device_info cml_gt2_info = {
}, \
GEN(11), \
ICL_COLORS, \
.dbuf.size = 2048, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.display.dbuf.size = 2048, \
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
@@ -942,8 +942,8 @@ static const struct intel_device_info adl_s_info = {
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \
}, \
.dbuf.size = 4096, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
.display.dbuf.size = 4096, \
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
BIT(DBUF_S4), \
.display.has_ddi = 1, \
.display.has_dmc = 1, \

9
drivers/gpu/drm/i915/intel_device_info.h
View File

@@ -225,15 +225,16 @@ struct intel_device_info {
u8 fbc_mask;
u8 abox_mask;
struct {
u16 size; /* in blocks */
u8 slice_mask;
} dbuf;
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
} display;
struct {
u16 size; /* in blocks */
u8 slice_mask;
} dbuf;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];

8
drivers/gpu/drm/i915/intel_pm.c
View File

@@ -4100,8 +4100,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
return INTEL_INFO(dev_priv)->dbuf.size /
hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
return INTEL_INFO(dev_priv)->display.dbuf.size /
hweight8(INTEL_INFO(dev_priv)->display.dbuf.slice_mask);
}
static void
@@ -4120,7 +4120,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
ddb->end = fls(slice_mask) * slice_size;
WARN_ON(ddb->start >= ddb->end);
WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
WARN_ON(ddb->end > INTEL_INFO(dev_priv)->display.dbuf.size);
}
static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
@@ -6095,7 +6095,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
INTEL_INFO(dev_priv)->dbuf.slice_mask,
INTEL_INFO(dev_priv)->display.dbuf.slice_mask,
str_yes_no(old_dbuf_state->joined_mbus),
str_yes_no(new_dbuf_state->joined_mbus));
}