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media: rockchip: vpss: fix switch scl params irq wrong

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Signed-off-by: Mingwei Yan <mingwei.yan@rock-chips.com>
Change-Id: I68bdd03f6bff412a131099eaba8d160e89a0b6fa
This commit is contained in:
Mingwei Yan
2024-06-19 18:46:38 +08:00
committed by Tao Huang
parent b04747085f
commit 0426bfc39b
2 changed files with 41 additions and 2 deletions
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28
drivers/media/platform/rockchip/vpss/stream.c
View File

@@ -1050,6 +1050,13 @@ static void poly_phase_scale(struct rkvpss_stream *stream, bool on, bool sync)
return;
}
/*config scl clk gate*/
if (in_w == out_w && in_h == out_h)
rkvpss_unite_clear_bits(dev, RKVPSS_VPSS_CLK_GATE, RKVPSS_SCL0_CKG_DIS);
else
rkvpss_unite_set_bits(dev, RKVPSS_VPSS_CLK_GATE, RKVPSS_SCL0_CKG_DIS,
RKVPSS_SCL0_CKG_DIS);
/* TODO diff for input and output format */
if (yuv420_in) {
in_div = 2;
@@ -1275,7 +1282,7 @@ static void bilinear_scale(struct rkvpss_stream *stream, bool on, bool sync)
u32 in_w = stream->crop.width;
u32 in_h = stream->crop.height;
u32 in_div, out_div;
u32 reg, val, ctrl = 0;
u32 reg, val, ctrl = 0, clk_mask = 0;
bool yuv420_in = false, yuv422_to_420 = false;
if (!on) {
@@ -1284,6 +1291,25 @@ static void bilinear_scale(struct rkvpss_stream *stream, bool on, bool sync)
return;
}
/*config scl clk gate*/
switch (stream->id) {
case RKVPSS_OUTPUT_CH1:
clk_mask = RKVPSS_SCL1_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH2:
clk_mask = RKVPSS_SCL2_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH3:
clk_mask = RKVPSS_SCL3_CKG_DIS;
break;
default:
return;
}
if (in_w == out_w && in_h == out_h)
rkvpss_unite_clear_bits(dev, RKVPSS_SCL0_CKG_DIS, clk_mask);
else
rkvpss_unite_set_bits(dev, RKVPSS_SCL0_CKG_DIS, clk_mask, clk_mask);
if (!dev->unite_mode) {
/* TODO diff for input and output format */
if (yuv420_in) {

15
drivers/media/platform/rockchip/vpss/vpss_offline.c
View File

@@ -268,7 +268,11 @@ static void poly_phase_scale(struct rkvpss_frame_cfg *frame_cfg,
if (in_w == out_w && in_h == out_w) {
rkvpss_hw_write(hw, RKVPSS_ZME_Y_SCL_CTRL, 0);
rkvpss_hw_write(hw, RKVPSS_ZME_UV_SCL_CTRL, 0);
rkvpss_hw_clear_bits(hw, RKVPSS_VPSS_CLK_GATE, RKVPSS_SCL0_CKG_DIS);
goto end;
} else {
rkvpss_hw_set_bits(hw, RKVPSS_VPSS_CLK_GATE, RKVPSS_SCL0_CKG_DIS,
RKVPSS_SCL0_CKG_DIS);
}
/* TODO diff for input and output format */
@@ -422,23 +426,32 @@ static void bilinear_scale(struct rkvpss_frame_cfg *frame_cfg,
struct rkvpss_hw_dev *hw = ofl->hw;
u32 in_w = cfg->crop_width, in_h = cfg->crop_height;
u32 out_w = cfg->scl_width, out_h = cfg->scl_height;
u32 reg_base, in_div, out_div, val, ctrl = 0;
u32 reg_base, in_div, out_div, val, ctrl = 0, clk_mask = 0;
bool yuv420_in = false, yuv422_to_420 = false;
switch (idx) {
case RKVPSS_OUTPUT_CH1:
reg_base = RKVPSS_SCALE1_BASE;
clk_mask = RKVPSS_SCL1_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH2:
reg_base = RKVPSS_SCALE2_BASE;
clk_mask = RKVPSS_SCL2_CKG_DIS;
break;
case RKVPSS_OUTPUT_CH3:
reg_base = RKVPSS_SCALE3_BASE;
clk_mask = RKVPSS_SCL3_CKG_DIS;
break;
default:
return;
}
/*config scl clk gate*/
if (in_w == out_w && in_h == out_h)
rkvpss_hw_clear_bits(hw, RKVPSS_VPSS_CLK_GATE, clk_mask);
else
rkvpss_hw_set_bits(hw, RKVPSS_VPSS_CLK_GATE, clk_mask, clk_mask);
if (!unite) {
if (in_w == out_w && in_h == out_w)
goto end;