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apply dos2unix to some of the AMLogic files so patch's applies cleanly

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Change-Id: I13f9faff4b386773f305f447a882457fa22888a7
This commit is contained in:
Mauro Ribeiro
2014-11-19 16:57:38 -02:00
committed by Dongjin Kim
parent bf3dc46b6d
commit 04cedbc4a0
7 changed files with 6330 additions and 6331 deletions
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6084
arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c
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File diff suppressed because it is too large Load Diff

462
arch/arm/mach-meson8b/hdmi_tx_hw/tvenc_conf.h
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@@ -1,231 +1,231 @@
typedef struct reg_s {
uint reg;
uint val;
} reg_t;
static reg_t hdmi_tvenc_regs_480i[] = {
/*1st col: recommmended, but eof/sof/vs_lines +/- 1 from spec; 2nd col: from simu */
{ENCP_VIDEO_MODE, 0 /*0 */ },
{ENCI_DE_H_BEGIN, 229 /*0xeb */ },
{ENCI_DE_H_END, 1669 /*0x68b */ },
{ENCI_DE_V_BEGIN_EVEN, 18 /*0x11 */ },
{ENCI_DE_V_END_EVEN, 258 /*0x101 */ },
{ENCI_DE_V_BEGIN_ODD, 19 /*0x12 */ },
{ENCI_DE_V_END_ODD, 259 /*0x102 */ },
{ENCI_DVI_HSO_BEGIN, 1707 /*0x6b1 */ },
{ENCI_DVI_HSO_END, 115 /*0x79 */ },
{ENCI_DVI_VSO_BLINE_EVN, 0 /*0x105 */ },
{ENCI_DVI_VSO_ELINE_EVN, 2 /*0x1 */ },
{ENCI_DVI_VSO_BEGIN_EVN, 1707 /*0x357 */ },
{ENCI_DVI_VSO_END_EVN, 1707 /*0x6b1 */ },
{ENCI_DVI_VSO_BLINE_ODD, 0 /*0x105 */ },
{ENCI_DVI_VSO_BEGIN_ODD, 849 /*0x6b1 */ },
{ENCI_DVI_VSO_ELINE_ODD, 3 /*0x2 */ },
{ENCI_DVI_VSO_END_ODD, 849 /*0x357 */ },
{VENC_DVI_SETTING, 0x809c /*0x809c*/ },
{VENC_DVI_SETTING_MORE, 0x0 /*0x0 */ },
{0,0}
};
static reg_t hdmi_tvenc_regs_576i[] = {
{ENCP_VIDEO_MODE, 0x00004000},
{ENCI_DE_H_BEGIN, 0x000000f9},
{ENCI_DE_H_END, 0x00000699},
{ENCI_DE_V_BEGIN_EVEN, 0x00000015},
{ENCI_DE_V_END_EVEN, 0x00000135},
{ENCI_DE_V_BEGIN_ODD, 0x00000016},
{ENCI_DE_V_END_ODD, 0x00000136},
{ENCI_DVI_HSO_BEGIN, 0x000006b1},
{ENCI_DVI_HSO_END, 0x0000006f},
{ENCI_DVI_VSO_BLINE_EVN, 0x00000137},
{ENCI_DVI_VSO_ELINE_EVN, 0x00000001},
{ENCI_DVI_VSO_BEGIN_EVN, 0x00000351},
{ENCI_DVI_VSO_END_EVN, 0x000006b1},
{ENCI_DVI_VSO_BLINE_ODD, 0x00000137},
{ENCI_DVI_VSO_BEGIN_ODD, 0x000006b1},
{ENCI_DVI_VSO_ELINE_ODD, 0x00000002},
{ENCI_DVI_VSO_END_ODD, 0x00000351},
{VENC_DVI_SETTING, 0x0000809c},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080i[] = {
{ENCP_VIDEO_MODE, 0x00005ffc},
{ENCP_DE_H_BEGIN, 0x00000210},
{ENCP_DE_H_END, 0x00001110},
{ENCP_DE_V_BEGIN_EVEN, 0x00000014},
{ENCP_DE_V_END_EVEN, 0x00000230},
{ENCP_DE_V_BEGIN_ODD, 0x00000247},
{ENCP_DE_V_END_ODD, 0x00000463},
{ENCP_DVI_HSO_BEGIN, 0x00000090},
{ENCP_DVI_HSO_END, 0x000000e8},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000090},
{ENCP_DVI_VSO_END_EVN, 0x00000090},
{ENCP_DVI_VSO_BLINE_ODD, 0x00000232},
{ENCP_DVI_VSO_ELINE_ODD, 0x00000237},
{ENCP_DVI_VSO_BEGIN_ODD, 0x00000928},
{ENCP_DVI_VSO_END_ODD, 0x00000928},
{VENC_DVI_SETTING, 0x000080ad},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080i50[] = {
{ENCP_VIDEO_MODE, 0x00005ffc},
{ENCP_DE_H_BEGIN, 0x00000210},
{ENCP_DE_H_END, 0x00001110},
{ENCP_DE_V_BEGIN_EVEN, 0x00000014},
{ENCP_DE_V_END_EVEN, 0x00000230},
{ENCP_DE_V_BEGIN_ODD, 0x00000247},
{ENCP_DE_V_END_ODD, 0x00000463},
{ENCP_DVI_HSO_BEGIN, 0x00000090},
{ENCP_DVI_HSO_END, 0x000000e8},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000090},
{ENCP_DVI_VSO_END_EVN, 0x00000090},
{ENCP_DVI_VSO_BLINE_ODD, 0x00000232},
{ENCP_DVI_VSO_ELINE_ODD, 0x00000237},
{ENCP_DVI_VSO_BEGIN_ODD, 0x00000ae0},
{ENCP_DVI_VSO_END_ODD, 0x00000ae0},
{VENC_DVI_SETTING, 0x000080ad},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_480p[] = {
{ENCP_VIDEO_MODE, /*0x4000 */ 0x00004000},
{ENCP_DE_H_BEGIN, /*0xdc */ 0x000000d7},
{ENCP_DE_H_END, /*0x67c */ 0x00000677},
{ENCP_DE_V_BEGIN_EVEN, /*0x2a */ 0x0000002b},
{ENCP_DE_V_END_EVEN, /*0x2a */ 0x0000020b},
{ENCP_DVI_HSO_BEGIN, /*0x69c */ 0x00000697},
{ENCP_DVI_HSO_END, /*0x64 */ 0x0000005f},
{ENCP_DVI_VSO_BLINE_EVN, /*0x5 */ 0x00000006},
{ENCP_DVI_VSO_ELINE_EVN, /*0xb */ 0x0000000c},
{ENCP_DVI_VSO_BEGIN_EVN, /*0x69c */ 0x00000697},
{ENCP_DVI_VSO_END_EVN, /*0x69c */ 0x00000697},
{VENC_DVI_SETTING_MORE, /*0x0 */ 0x00000000},
{VENC_DVI_SETTING, /*0x80ad */ 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_576p[] = {
{ENCP_VIDEO_MODE, 0x00004000},
{ENCP_DE_H_BEGIN, 0x000000ef},
{ENCP_DE_H_END, 0x0000068f},
{ENCP_DE_V_BEGIN_EVEN, 0x0000002d},
{ENCP_DE_V_END_EVEN, 0x0000026d},
{ENCP_DVI_HSO_BEGIN, 0x000006a7},
{ENCP_DVI_HSO_END, 0x00000067},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x000006a7},
{ENCP_DVI_VSO_END_EVN, 0x000006a7},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_720p[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x0000028a},
{ENCP_DE_H_END, 0x00000c8a},
{ENCP_DE_V_BEGIN_EVEN, 0x0000001d},
{ENCP_DE_V_END_EVEN, 0x000002ed},
{ENCP_DVI_HSO_BEGIN, 0x00000082},
{ENCP_DVI_HSO_END, 0x000000d2},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000004},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000009},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000082},
{ENCP_DVI_VSO_END_EVN, 0x00000082},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080p[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x00000112},
{ENCP_DE_H_END, 0x00000892},
{ENCP_DE_V_BEGIN_EVEN, 0x00000029},
{ENCP_DE_V_END_EVEN, 0x00000461},
{ENCP_DVI_HSO_BEGIN, 0x00000052},
{ENCP_DVI_HSO_END, 0x0000007e},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052},
{ENCP_DVI_VSO_END_EVN, 0x00000052},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x0000809d},
{0,0}
};
static reg_t hdmi_tvenc_regs_720p50[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x0000028a},
{ENCP_DE_H_END, 0x00000c8a},
{ENCP_DE_V_BEGIN_EVEN, 0x0000001d},
{ENCP_DE_V_END_EVEN, 0x000002ed},
{ENCP_DVI_HSO_BEGIN, 0x00000082},
{ENCP_DVI_HSO_END, 0x000000d2},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000004},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000009},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000082},
{ENCP_DVI_VSO_END_EVN, 0x00000082},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080p50[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x00000112},
{ENCP_DE_H_END, 0x00000892},
{ENCP_DE_V_BEGIN_EVEN, 0x00000029},
{ENCP_DE_V_END_EVEN, 0x00000461},
{ENCP_DVI_HSO_BEGIN, 0x00000052},
{ENCP_DVI_HSO_END, 0x0000007e},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052},
{ENCP_DVI_VSO_END_EVN, 0x00000052},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x0000809d},
{0,0}
};
typedef struct hdmi_tvenc_config_
{
int vic;
reg_t* reg_set;
}hdmi_tvenc_config_t;
static const hdmi_tvenc_config_t hdmi_tvenc_configs[] = {
{HDMI_640x480p60 , NULL },
{HDMI_480p60, hdmi_tvenc_regs_480p},
{HDMI_480p60_16x9, hdmi_tvenc_regs_480p},
{HDMI_720p60, hdmi_tvenc_regs_720p},
{HDMI_1080i60, hdmi_tvenc_regs_1080i},
{HDMI_480i60, hdmi_tvenc_regs_480i},
{HDMI_480i60_16x9, hdmi_tvenc_regs_480i},
{HDMI_1440x480p60 , NULL },
{HDMI_1440x480p60_16x9 , NULL },
{HDMI_1080p60 , hdmi_tvenc_regs_1080p},
{HDMI_576p50, hdmi_tvenc_regs_576p},
{HDMI_576p50_16x9, hdmi_tvenc_regs_576p},
{HDMI_720p50, hdmi_tvenc_regs_720p50},
{HDMI_1080i50, hdmi_tvenc_regs_1080i50},
{HDMI_576i50, hdmi_tvenc_regs_576i},
{HDMI_576i50_16x9, hdmi_tvenc_regs_576i},
{HDMI_1080p50 , hdmi_tvenc_regs_1080p50},
{HDMI_1080p24, hdmi_tvenc_regs_1080p},
{HDMI_1080p25, hdmi_tvenc_regs_1080p},
{HDMI_1080p30, hdmi_tvenc_regs_1080p},
{HDMI_Unkown, NULL},
};
typedef struct reg_s {
uint reg;
uint val;
} reg_t;
static reg_t hdmi_tvenc_regs_480i[] = {
/*1st col: recommmended, but eof/sof/vs_lines +/- 1 from spec; 2nd col: from simu */
{ENCP_VIDEO_MODE, 0 /*0 */ },
{ENCI_DE_H_BEGIN, 229 /*0xeb */ },
{ENCI_DE_H_END, 1669 /*0x68b */ },
{ENCI_DE_V_BEGIN_EVEN, 18 /*0x11 */ },
{ENCI_DE_V_END_EVEN, 258 /*0x101 */ },
{ENCI_DE_V_BEGIN_ODD, 19 /*0x12 */ },
{ENCI_DE_V_END_ODD, 259 /*0x102 */ },
{ENCI_DVI_HSO_BEGIN, 1707 /*0x6b1 */ },
{ENCI_DVI_HSO_END, 115 /*0x79 */ },
{ENCI_DVI_VSO_BLINE_EVN, 0 /*0x105 */ },
{ENCI_DVI_VSO_ELINE_EVN, 2 /*0x1 */ },
{ENCI_DVI_VSO_BEGIN_EVN, 1707 /*0x357 */ },
{ENCI_DVI_VSO_END_EVN, 1707 /*0x6b1 */ },
{ENCI_DVI_VSO_BLINE_ODD, 0 /*0x105 */ },
{ENCI_DVI_VSO_BEGIN_ODD, 849 /*0x6b1 */ },
{ENCI_DVI_VSO_ELINE_ODD, 3 /*0x2 */ },
{ENCI_DVI_VSO_END_ODD, 849 /*0x357 */ },
{VENC_DVI_SETTING, 0x809c /*0x809c*/ },
{VENC_DVI_SETTING_MORE, 0x0 /*0x0 */ },
{0,0}
};
static reg_t hdmi_tvenc_regs_576i[] = {
{ENCP_VIDEO_MODE, 0x00004000},
{ENCI_DE_H_BEGIN, 0x000000f9},
{ENCI_DE_H_END, 0x00000699},
{ENCI_DE_V_BEGIN_EVEN, 0x00000015},
{ENCI_DE_V_END_EVEN, 0x00000135},
{ENCI_DE_V_BEGIN_ODD, 0x00000016},
{ENCI_DE_V_END_ODD, 0x00000136},
{ENCI_DVI_HSO_BEGIN, 0x000006b1},
{ENCI_DVI_HSO_END, 0x0000006f},
{ENCI_DVI_VSO_BLINE_EVN, 0x00000137},
{ENCI_DVI_VSO_ELINE_EVN, 0x00000001},
{ENCI_DVI_VSO_BEGIN_EVN, 0x00000351},
{ENCI_DVI_VSO_END_EVN, 0x000006b1},
{ENCI_DVI_VSO_BLINE_ODD, 0x00000137},
{ENCI_DVI_VSO_BEGIN_ODD, 0x000006b1},
{ENCI_DVI_VSO_ELINE_ODD, 0x00000002},
{ENCI_DVI_VSO_END_ODD, 0x00000351},
{VENC_DVI_SETTING, 0x0000809c},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080i[] = {
{ENCP_VIDEO_MODE, 0x00005ffc},
{ENCP_DE_H_BEGIN, 0x00000210},
{ENCP_DE_H_END, 0x00001110},
{ENCP_DE_V_BEGIN_EVEN, 0x00000014},
{ENCP_DE_V_END_EVEN, 0x00000230},
{ENCP_DE_V_BEGIN_ODD, 0x00000247},
{ENCP_DE_V_END_ODD, 0x00000463},
{ENCP_DVI_HSO_BEGIN, 0x00000090},
{ENCP_DVI_HSO_END, 0x000000e8},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000090},
{ENCP_DVI_VSO_END_EVN, 0x00000090},
{ENCP_DVI_VSO_BLINE_ODD, 0x00000232},
{ENCP_DVI_VSO_ELINE_ODD, 0x00000237},
{ENCP_DVI_VSO_BEGIN_ODD, 0x00000928},
{ENCP_DVI_VSO_END_ODD, 0x00000928},
{VENC_DVI_SETTING, 0x000080ad},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080i50[] = {
{ENCP_VIDEO_MODE, 0x00005ffc},
{ENCP_DE_H_BEGIN, 0x00000210},
{ENCP_DE_H_END, 0x00001110},
{ENCP_DE_V_BEGIN_EVEN, 0x00000014},
{ENCP_DE_V_END_EVEN, 0x00000230},
{ENCP_DE_V_BEGIN_ODD, 0x00000247},
{ENCP_DE_V_END_ODD, 0x00000463},
{ENCP_DVI_HSO_BEGIN, 0x00000090},
{ENCP_DVI_HSO_END, 0x000000e8},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000090},
{ENCP_DVI_VSO_END_EVN, 0x00000090},
{ENCP_DVI_VSO_BLINE_ODD, 0x00000232},
{ENCP_DVI_VSO_ELINE_ODD, 0x00000237},
{ENCP_DVI_VSO_BEGIN_ODD, 0x00000ae0},
{ENCP_DVI_VSO_END_ODD, 0x00000ae0},
{VENC_DVI_SETTING, 0x000080ad},
{VENC_DVI_SETTING_MORE, 0x00000000},
{0,0}
};
static reg_t hdmi_tvenc_regs_480p[] = {
{ENCP_VIDEO_MODE, /*0x4000 */ 0x00004000},
{ENCP_DE_H_BEGIN, /*0xdc */ 0x000000d7},
{ENCP_DE_H_END, /*0x67c */ 0x00000677},
{ENCP_DE_V_BEGIN_EVEN, /*0x2a */ 0x0000002b},
{ENCP_DE_V_END_EVEN, /*0x2a */ 0x0000020b},
{ENCP_DVI_HSO_BEGIN, /*0x69c */ 0x00000697},
{ENCP_DVI_HSO_END, /*0x64 */ 0x0000005f},
{ENCP_DVI_VSO_BLINE_EVN, /*0x5 */ 0x00000006},
{ENCP_DVI_VSO_ELINE_EVN, /*0xb */ 0x0000000c},
{ENCP_DVI_VSO_BEGIN_EVN, /*0x69c */ 0x00000697},
{ENCP_DVI_VSO_END_EVN, /*0x69c */ 0x00000697},
{VENC_DVI_SETTING_MORE, /*0x0 */ 0x00000000},
{VENC_DVI_SETTING, /*0x80ad */ 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_576p[] = {
{ENCP_VIDEO_MODE, 0x00004000},
{ENCP_DE_H_BEGIN, 0x000000ef},
{ENCP_DE_H_END, 0x0000068f},
{ENCP_DE_V_BEGIN_EVEN, 0x0000002d},
{ENCP_DE_V_END_EVEN, 0x0000026d},
{ENCP_DVI_HSO_BEGIN, 0x000006a7},
{ENCP_DVI_HSO_END, 0x00000067},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x000006a7},
{ENCP_DVI_VSO_END_EVN, 0x000006a7},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_720p[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x0000028a},
{ENCP_DE_H_END, 0x00000c8a},
{ENCP_DE_V_BEGIN_EVEN, 0x0000001d},
{ENCP_DE_V_END_EVEN, 0x000002ed},
{ENCP_DVI_HSO_BEGIN, 0x00000082},
{ENCP_DVI_HSO_END, 0x000000d2},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000004},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000009},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000082},
{ENCP_DVI_VSO_END_EVN, 0x00000082},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080p[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x00000112},
{ENCP_DE_H_END, 0x00000892},
{ENCP_DE_V_BEGIN_EVEN, 0x00000029},
{ENCP_DE_V_END_EVEN, 0x00000461},
{ENCP_DVI_HSO_BEGIN, 0x00000052},
{ENCP_DVI_HSO_END, 0x0000007e},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052},
{ENCP_DVI_VSO_END_EVN, 0x00000052},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x0000809d},
{0,0}
};
static reg_t hdmi_tvenc_regs_720p50[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x0000028a},
{ENCP_DE_H_END, 0x00000c8a},
{ENCP_DE_V_BEGIN_EVEN, 0x0000001d},
{ENCP_DE_V_END_EVEN, 0x000002ed},
{ENCP_DVI_HSO_BEGIN, 0x00000082},
{ENCP_DVI_HSO_END, 0x000000d2},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000004},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000009},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000082},
{ENCP_DVI_VSO_END_EVN, 0x00000082},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x000080ad},
{0,0}
};
static reg_t hdmi_tvenc_regs_1080p50[] = {
{ENCP_VIDEO_MODE, 0x00004040},
{ENCP_DE_H_BEGIN, 0x00000112},
{ENCP_DE_H_END, 0x00000892},
{ENCP_DE_V_BEGIN_EVEN, 0x00000029},
{ENCP_DE_V_END_EVEN, 0x00000461},
{ENCP_DVI_HSO_BEGIN, 0x00000052},
{ENCP_DVI_HSO_END, 0x0000007e},
{ENCP_DVI_VSO_BLINE_EVN, 0x00000000},
{ENCP_DVI_VSO_ELINE_EVN, 0x00000005},
{ENCP_DVI_VSO_BEGIN_EVN, 0x00000052},
{ENCP_DVI_VSO_END_EVN, 0x00000052},
{VENC_DVI_SETTING_MORE, 0x00000000},
{VENC_DVI_SETTING, 0x0000809d},
{0,0}
};
typedef struct hdmi_tvenc_config_
{
int vic;
reg_t* reg_set;
}hdmi_tvenc_config_t;
static const hdmi_tvenc_config_t hdmi_tvenc_configs[] = {
{HDMI_640x480p60 , NULL },
{HDMI_480p60, hdmi_tvenc_regs_480p},
{HDMI_480p60_16x9, hdmi_tvenc_regs_480p},
{HDMI_720p60, hdmi_tvenc_regs_720p},
{HDMI_1080i60, hdmi_tvenc_regs_1080i},
{HDMI_480i60, hdmi_tvenc_regs_480i},
{HDMI_480i60_16x9, hdmi_tvenc_regs_480i},
{HDMI_1440x480p60 , NULL },
{HDMI_1440x480p60_16x9 , NULL },
{HDMI_1080p60 , hdmi_tvenc_regs_1080p},
{HDMI_576p50, hdmi_tvenc_regs_576p},
{HDMI_576p50_16x9, hdmi_tvenc_regs_576p},
{HDMI_720p50, hdmi_tvenc_regs_720p50},
{HDMI_1080i50, hdmi_tvenc_regs_1080i50},
{HDMI_576i50, hdmi_tvenc_regs_576i},
{HDMI_576i50_16x9, hdmi_tvenc_regs_576i},
{HDMI_1080p50 , hdmi_tvenc_regs_1080p50},
{HDMI_1080p24, hdmi_tvenc_regs_1080p},
{HDMI_1080p25, hdmi_tvenc_regs_1080p},
{HDMI_1080p30, hdmi_tvenc_regs_1080p},
{HDMI_Unkown, NULL},
};

1342
drivers/amlogic/display/vout/enc_clk_config.c
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114
drivers/amlogic/display/vout/tvmode.h
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@@ -1,57 +1,57 @@
/*
* Amlogic Apollo
* frame buffer driver
*
* Copyright (C) 2009 Amlogic, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Author: Tim Yao <timyao@amlogic.com>
*
*/
#ifndef TVMODE_H
#define TVMODE_H
typedef enum {
TVMODE_480I = 0,
TVMODE_480I_RPT ,
TVMODE_480CVBS,
TVMODE_480P ,
TVMODE_480P_RPT ,
TVMODE_576I ,
TVMODE_576I_RPT ,
TVMODE_576CVBS,
TVMODE_576P ,
TVMODE_576P_RPT ,
TVMODE_720P ,
TVMODE_1080I ,
TVMODE_1080P ,
TVMODE_720P_50HZ ,
TVMODE_1080I_50HZ ,
TVMODE_1080P_50HZ ,
TVMODE_1080P_24HZ ,
TVMODE_4K2K_30HZ ,
TVMODE_4K2K_25HZ ,
TVMODE_4K2K_24HZ ,
TVMODE_4K2K_SMPTE ,
TVMODE_VGA ,
TVMODE_SVGA,
TVMODE_XGA,
TVMODE_SXGA,
TVMODE_MAX
} tvmode_t;
#endif /* TVMODE_H */
/*
* Amlogic Apollo
* frame buffer driver
*
* Copyright (C) 2009 Amlogic, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Author: Tim Yao <timyao@amlogic.com>
*
*/
#ifndef TVMODE_H
#define TVMODE_H
typedef enum {
TVMODE_480I = 0,
TVMODE_480I_RPT ,
TVMODE_480CVBS,
TVMODE_480P ,
TVMODE_480P_RPT ,
TVMODE_576I ,
TVMODE_576I_RPT ,
TVMODE_576CVBS,
TVMODE_576P ,
TVMODE_576P_RPT ,
TVMODE_720P ,
TVMODE_1080I ,
TVMODE_1080P ,
TVMODE_720P_50HZ ,
TVMODE_1080I_50HZ ,
TVMODE_1080P_50HZ ,
TVMODE_1080P_24HZ ,
TVMODE_4K2K_30HZ ,
TVMODE_4K2K_25HZ ,
TVMODE_4K2K_24HZ ,
TVMODE_4K2K_SMPTE ,
TVMODE_VGA ,
TVMODE_SVGA,
TVMODE_XGA,
TVMODE_SXGA,
TVMODE_MAX
} tvmode_t;
#endif /* TVMODE_H */

3139
drivers/amlogic/hdmi/hdmi_tx/hdmi_tx_edid.c
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1360
include/linux/amlogic/hdmi_tx/hdmi_info_global.h
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File diff suppressed because it is too large Load Diff

160
include/linux/amlogic/vout/vinfo.h
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@@ -1,80 +1,80 @@
/*
* Amlogic Apollo
* frame buffer driver
*
* Copyright (C) 2009 Amlogic, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Author: Tim Yao <timyao@amlogic.com>
*
*/
#ifndef VINFO_H
#define VINFO_H
//the MSB is represent vmode set by logo
#define VMODE_LOGO_BIT_MASK 0x8000
#define VMODE_MODE_BIT_MASK 0xff
typedef enum {
VMODE_480I = 0,
VMODE_480I_RPT ,
VMODE_480CVBS,
VMODE_480P ,
VMODE_480P_RPT ,
VMODE_576I ,
VMODE_576I_RPT ,
VMODE_576CVBS ,
VMODE_576P ,
VMODE_576P_RPT ,
VMODE_720P ,
VMODE_1080I ,
VMODE_1080P ,
VMODE_720P_50HZ ,
VMODE_1080I_50HZ ,
VMODE_1080P_50HZ ,
VMODE_1080P_24HZ ,
VMODE_4K2K_30HZ ,
VMODE_4K2K_25HZ ,
VMODE_4K2K_24HZ ,
VMODE_4K2K_SMPTE,
VMODE_VGA,
VMODE_SVGA,
VMODE_XGA,
VMODE_SXGA,
VMODE_LCD ,
VMODE_LVDS_1080P,
VMODE_LVDS_1080P_50HZ,
VMODE_LVDS_768P,
VMODE_MAX,
VMODE_INIT_NULL,
VMODE_MASK = 0xFF,
} vmode_t;
typedef struct {
char *name;
vmode_t mode;
u32 width;
u32 height;
u32 field_height;
u32 aspect_ratio_num;
u32 aspect_ratio_den;
u32 sync_duration_num;
u32 sync_duration_den;
u32 screen_real_width;
u32 screen_real_height;
u32 video_clk;
} vinfo_t;
#endif /* TVMODE_H */
/*
* Amlogic Apollo
* frame buffer driver
*
* Copyright (C) 2009 Amlogic, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Author: Tim Yao <timyao@amlogic.com>
*
*/
#ifndef VINFO_H
#define VINFO_H
//the MSB is represent vmode set by logo
#define VMODE_LOGO_BIT_MASK 0x8000
#define VMODE_MODE_BIT_MASK 0xff
typedef enum {
VMODE_480I = 0,
VMODE_480I_RPT ,
VMODE_480CVBS,
VMODE_480P ,
VMODE_480P_RPT ,
VMODE_576I ,
VMODE_576I_RPT ,
VMODE_576CVBS ,
VMODE_576P ,
VMODE_576P_RPT ,
VMODE_720P ,
VMODE_1080I ,
VMODE_1080P ,
VMODE_720P_50HZ ,
VMODE_1080I_50HZ ,
VMODE_1080P_50HZ ,
VMODE_1080P_24HZ ,
VMODE_4K2K_30HZ ,
VMODE_4K2K_25HZ ,
VMODE_4K2K_24HZ ,
VMODE_4K2K_SMPTE,
VMODE_VGA,
VMODE_SVGA,
VMODE_XGA,
VMODE_SXGA,
VMODE_LCD ,
VMODE_LVDS_1080P,
VMODE_LVDS_1080P_50HZ,
VMODE_LVDS_768P,
VMODE_MAX,
VMODE_INIT_NULL,
VMODE_MASK = 0xFF,
} vmode_t;
typedef struct {
char *name;
vmode_t mode;
u32 width;
u32 height;
u32 field_height;
u32 aspect_ratio_num;
u32 aspect_ratio_den;
u32 sync_duration_num;
u32 sync_duration_den;
u32 screen_real_width;
u32 screen_real_height;
u32 video_clk;
} vinfo_t;
#endif /* TVMODE_H */