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clk: rockchip: fix up the pll-type for rk3328

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fix up the pll type pll_rk3328 description and use.
add the other parts handling parents,like num_parents check
and the init.num_parents parameter.
add ctx->grf.

Change-Id: I17f1b0dc4b8286817f587e02fdea39f2d886f3d0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-01-05 14:39:36 +08:00
committed by Huang, Tao
parent 58e23d3e43
commit 0536f308d8
2 changed files with 9 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/clk/rockchip/clk-pll.c
View File

@@ -1234,7 +1234,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
struct clk *pll_clk, *mux_clk;
char pll_name[20];
if (num_parents != 2) {
if ((pll_type != pll_rk3328 && num_parents != 2) ||
(pll_type == pll_rk3328 && num_parents != 1)) {
pr_err("%s: needs two parent clocks\n", __func__);
return ERR_PTR(-EINVAL);
}
@@ -1275,7 +1276,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
init.flags = CLK_SET_RATE_PARENT;
init.ops = pll->pll_mux_ops;
init.parent_names = pll_parents;
init.num_parents = ARRAY_SIZE(pll_parents);
if (pll_type == pll_rk3328)
init.num_parents = 2;
else
init.num_parents = ARRAY_SIZE(pll_parents);
mux_clk = clk_register(NULL, &pll_mux->hw);
if (IS_ERR(mux_clk))
@@ -1309,6 +1313,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
switch (pll_type) {
case pll_rk3036:
case pll_rk3328:
if (!pll->rate_table)
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
@@ -1320,12 +1325,6 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
else
init.ops = &rockchip_rk3066_pll_clk_ops;
break;
case pll_rk3328:
if (!pll->rate_table)
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
init.ops = &rockchip_rk3036_pll_clk_ops;
break;
case pll_rk3366:
if (!pll->rate_table)
init.ops = &rockchip_rk3366_pll_clk_norate_ops;

2
drivers/clk/rockchip/clk.c
View File

@@ -348,6 +348,8 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
ctx->cru_node = np;
ctx->grf = ERR_PTR(-EPROBE_DEFER);
spin_lock_init(&ctx->lock);
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
return ctx;