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amvecm: dnlp new c curve and interface [1/4]

Browse Source 
PD#SWPL-5338

Problem:
dnlp new c curve and interface

Solution:
dnlp new c curve and interface

Verify:
x301

Change-Id: I7a221b6c5546873ebc3c3182d4856d57ffc3df48
Signed-off-by: Bencheng Jing <bencheng.jing@amlogic.com>
This commit is contained in:
Bencheng Jing
2019-03-21 22:45:16 +08:00
committed by Tao Zeng
parent 4554f63c54
commit 06020b9544
5 changed files with 463 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

201
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -1976,6 +1976,101 @@ static ssize_t amvecm_dnlp_debug_store(struct class *cla,
else
pr_info("%d\n", wext_gain_copy[val]);
}
} else if (!strcmp(parm[1], "adp_thrd")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
for (i = 0; i < 33; i++)
d_convert_str(adp_thrd_copy[i],
i, stemp, 4, 10);
pr_info("%s\n", stemp);
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
if ((val > 32) || (val < 0))
pr_info("error cmd\n");
else
pr_info("%d\n", adp_thrd_copy[val]);
}
} else if (!strcmp(parm[1], "reg_blk_boost_12")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
for (i = 0; i < 13; i++)
d_convert_str(reg_blk_boost_12_copy[i],
i, stemp, 4, 10);
pr_info("%s\n", stemp);
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
if ((val > 12) || (val < 0))
pr_info("error cmd\n");
else
pr_info("%d\n",
reg_blk_boost_12_copy[val]);
}
} else if (!strcmp(parm[1], "reg_adp_ofset_20")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
for (i = 0; i < 20; i++)
d_convert_str(reg_adp_ofset_20_copy[i],
i, stemp, 4, 10);
pr_info("%s\n", stemp);
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
if ((val > 19) || (val < 0))
pr_info("error cmd\n");
else
pr_info("%d\n",
reg_adp_ofset_20_copy[val]);
}
} else if (!strcmp(parm[1], "reg_mono_protect")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
for (i = 0; i < 6; i++)
d_convert_str(reg_mono_protect_copy[i],
i, stemp, 4, 10);
pr_info("%s\n", stemp);
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
if ((val > 5) || (val < 0))
pr_info("error cmd\n");
else
pr_info("%d\n",
reg_mono_protect_copy[val]);
}
} else if (!strcmp(parm[1], "reg_trend_wht_expand_lut8")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
for (i = 0; i < 9; i++)
d_convert_str(
reg_trend_wht_expand_lut8_copy[i],
i, stemp, 4, 10);
pr_info("%s\n", stemp);
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
if ((val > 8) || (val < 0))
pr_info("error cmd\n");
else
pr_info("%d\n",
reg_trend_wht_expand_lut8_copy[val]);
}
} else if (!strcmp(parm[1], "ve_dnlp_tgt")) {
/*read only curve*/
if (parm[2] == NULL) {
@@ -2198,6 +2293,112 @@ static ssize_t amvecm_dnlp_debug_store(struct class *cla,
else
wext_gain_copy[num] = val;
}
} else if (!strcmp(parm[1], "adp_thrd")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
str_sapr_to_d(parm[3], curve_val, 5);
for (i = 0; i < 33; i++)
adp_thrd_copy[i] = curve_val[i];
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
num = val;
if (kstrtoul(parm[3], 10, &val) < 0)
goto free_buf;
if (num > 32)
pr_info("error cmd\n");
else
adp_thrd_copy[num] = val;
}
} else if (!strcmp(parm[1], "reg_blk_boost_12")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
str_sapr_to_d(parm[3], curve_val, 5);
for (i = 0; i < 13; i++)
reg_blk_boost_12_copy[i] = curve_val[i];
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
num = val;
if (kstrtoul(parm[3], 10, &val) < 0)
goto free_buf;
if (num > 12)
pr_info("error cmd\n");
else
reg_blk_boost_12_copy[num] = val;
}
} else if (!strcmp(parm[1], "reg_adp_ofset_20")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
str_sapr_to_d(parm[3], curve_val, 5);
for (i = 0; i < 20; i++)
reg_adp_ofset_20_copy[i] = curve_val[i];
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
num = val;
if (kstrtoul(parm[3], 10, &val) < 0)
goto free_buf;
if (num > 19)
pr_info("error cmd\n");
else
reg_adp_ofset_20_copy[num] = val;
}
} else if (!strcmp(parm[1], "reg_mono_protect")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
str_sapr_to_d(parm[3], curve_val, 5);
for (i = 0; i < 6; i++)
reg_mono_protect_copy[i] = curve_val[i];
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
num = val;
if (kstrtoul(parm[3], 10, &val) < 0)
goto free_buf;
if (num > 5)
pr_info("error cmd\n");
else
reg_mono_protect_copy[num] = val;
}
} else if (!strcmp(parm[1], "reg_trend_wht_expand_lut8")) {
if (parm[2] == NULL) {
pr_info("error cmd\n");
goto free_buf;
} else if (!strcmp(parm[2], "all")) {
str_sapr_to_d(parm[3], curve_val, 5);
for (i = 0; i < 9; i++)
reg_trend_wht_expand_lut8_copy[i] =
curve_val[i];
} else {
if (kstrtoul(parm[2], 10, &val) < 0)
goto free_buf;
num = val;
if (kstrtoul(parm[3], 10, &val) < 0)
goto free_buf;
if (num > 8)
pr_info("error cmd\n");
else
reg_trend_wht_expand_lut8_copy[num] = val;
}
}
} else if (!strcmp(parm[0], "ro")) {
if (!strcmp(parm[1], "luma_avg4"))

26
drivers/amlogic/media/enhancement/amvecm/dnlp_algorithm/dnlp_alg.h
View File

@@ -76,6 +76,26 @@ struct param_for_dnlp_s {
unsigned int dnlp_scurv_hgh1_th;
unsigned int dnlp_scurv_hgh2_th;
unsigned int dnlp_mtdrate_adp_en;
unsigned int dnlp_clahe_method;
unsigned int dnlp_ble_en;
unsigned int dnlp_norm;
unsigned int dnlp_scn_chg_th;
unsigned int dnlp_step_th;
unsigned int dnlp_iir_step_mux;
unsigned int dnlp_single_bin_bw;
unsigned int dnlp_single_bin_method;
unsigned int dnlp_reg_max_slop_1st;
unsigned int dnlp_reg_max_slop_mid;
unsigned int dnlp_reg_max_slop_fin;
unsigned int dnlp_reg_min_slop_1st;
unsigned int dnlp_reg_min_slop_mid;
unsigned int dnlp_reg_min_slop_fin;
unsigned int dnlp_reg_trend_wht_expand_mode;
unsigned int dnlp_reg_trend_blk_expand_mode;
unsigned int dnlp_ve_hist_cur_gain;
unsigned int dnlp_ve_hist_cur_gain_precise;
unsigned int dnlp_reg_mono_binrang_st;
unsigned int dnlp_reg_mono_binrang_ed;
};
struct dnlp_alg_input_param_s {
@@ -112,8 +132,12 @@ struct dnlp_dbg_rw_param_s {
int *dnlp_scurv_hgh2;
int *gain_var_lut49;
int *wext_gain;
int *adp_thrd;
int *reg_blk_boost_12;
int *reg_adp_ofset_20;
int *reg_mono_protect;
int *reg_trend_wht_expand_lut8;
};
struct dnlp_dbg_print_s {
int *dnlp_printk;
};

179
drivers/amlogic/media/enhancement/amvecm/dnlp_cal.c
View File

@@ -69,6 +69,11 @@ int *dnlp_scurv_hgh1_copy;
int *dnlp_scurv_hgh2_copy;
int *gain_var_lut49_copy;
int *wext_gain_copy;
int *adp_thrd_copy;
int *reg_blk_boost_12_copy;
int *reg_adp_ofset_20_copy;
int *reg_mono_protect_copy;
int *reg_trend_wht_expand_lut8_copy;
int *ro_luma_avg4_copy;
int *ro_var_d8_copy;
@@ -154,6 +159,29 @@ struct dnlp_parse_cmd_s dnlp_parse_cmd[] = {
{"scurv_hgh1_th", &(dnlp_alg_param.dnlp_scurv_hgh1_th)},
{"scurv_hgh2_th", &(dnlp_alg_param.dnlp_scurv_hgh2_th)},
{"mtdrate_adp_en", &(dnlp_alg_param.dnlp_mtdrate_adp_en)},
{"clahe_method", &(dnlp_alg_param.dnlp_clahe_method)},
{"ble_en", &(dnlp_alg_param.dnlp_ble_en)},
{"norm", &(dnlp_alg_param.dnlp_norm)},
{"scn_chg_th", &(dnlp_alg_param.dnlp_scn_chg_th)},
{"step_th", &(dnlp_alg_param.dnlp_step_th)},
{"iir_step_mux", &(dnlp_alg_param.dnlp_iir_step_mux)},
{"single_bin_bw", &(dnlp_alg_param.dnlp_single_bin_bw)},
{"single_bin_method", &(dnlp_alg_param.dnlp_single_bin_method)},
{"reg_max_slop_1st", &(dnlp_alg_param.dnlp_reg_max_slop_1st)},
{"reg_max_slop_mid", &(dnlp_alg_param.dnlp_reg_max_slop_mid)},
{"reg_max_slop_fin", &(dnlp_alg_param.dnlp_reg_max_slop_fin)},
{"reg_min_slop_1st", &(dnlp_alg_param.dnlp_reg_min_slop_1st)},
{"reg_min_slop_mid", &(dnlp_alg_param.dnlp_reg_min_slop_mid)},
{"reg_min_slop_fin", &(dnlp_alg_param.dnlp_reg_min_slop_fin)},
{"reg_trend_wht_expand_mode",
&(dnlp_alg_param.dnlp_reg_trend_wht_expand_mode)},
{"reg_trend_blk_expand_mode",
&(dnlp_alg_param.dnlp_reg_trend_blk_expand_mode)},
{"ve_hist_cur_gain", &(dnlp_alg_param.dnlp_ve_hist_cur_gain)},
{"ve_hist_cur_gain_precise",
&(dnlp_alg_param.dnlp_ve_hist_cur_gain_precise)},
{"reg_mono_binrang_st", &(dnlp_alg_param.dnlp_reg_mono_binrang_st)},
{"reg_mono_binrang_ed", &(dnlp_alg_param.dnlp_reg_mono_binrang_ed)},
{"", NULL}
};
@@ -166,6 +194,12 @@ void dnlp_alg_param_copy(void)
dnlp_scurv_hgh2_copy = dnlp_dbg_rw_param->dnlp_scurv_hgh2;
gain_var_lut49_copy = dnlp_dbg_rw_param->gain_var_lut49;
wext_gain_copy = dnlp_dbg_rw_param->wext_gain;
adp_thrd_copy = dnlp_dbg_rw_param->adp_thrd;
reg_blk_boost_12_copy = dnlp_dbg_rw_param->reg_blk_boost_12;
reg_adp_ofset_20_copy = dnlp_dbg_rw_param->reg_adp_ofset_20;
reg_mono_protect_copy = dnlp_dbg_rw_param->reg_mono_protect;
reg_trend_wht_expand_lut8_copy =
dnlp_dbg_rw_param->reg_trend_wht_expand_lut8;
ro_luma_avg4_copy = dnlp_dbg_ro_param->ro_luma_avg4;
ro_var_d8_copy = dnlp_dbg_ro_param->ro_var_d8;
@@ -257,6 +291,26 @@ void dnlp_alg_param_init(void)
dnlp_alg_param.dnlp_scurv_hgh1_th = 176;
dnlp_alg_param.dnlp_scurv_hgh2_th = 240;
dnlp_alg_param.dnlp_mtdrate_adp_en = 1;
dnlp_alg_param.dnlp_clahe_method = 1;
dnlp_alg_param.dnlp_ble_en = 1;
dnlp_alg_param.dnlp_norm = 10;
dnlp_alg_param.dnlp_scn_chg_th = 48;
dnlp_alg_param.dnlp_step_th = 1;
dnlp_alg_param.dnlp_iir_step_mux = 1;
dnlp_alg_param.dnlp_single_bin_bw = 2;
dnlp_alg_param.dnlp_single_bin_method = 1;
dnlp_alg_param.dnlp_reg_max_slop_1st = 614;
dnlp_alg_param.dnlp_reg_max_slop_mid = 400;
dnlp_alg_param.dnlp_reg_max_slop_fin = 614;
dnlp_alg_param.dnlp_reg_min_slop_1st = 77;
dnlp_alg_param.dnlp_reg_min_slop_mid = 144;
dnlp_alg_param.dnlp_reg_min_slop_fin = 77;
dnlp_alg_param.dnlp_reg_trend_wht_expand_mode = 2;
dnlp_alg_param.dnlp_reg_trend_blk_expand_mode = 2;
dnlp_alg_param.dnlp_ve_hist_cur_gain = 8;
dnlp_alg_param.dnlp_ve_hist_cur_gain_precise = 8;
dnlp_alg_param.dnlp_reg_mono_binrang_st = 7;
dnlp_alg_param.dnlp_reg_mono_binrang_ed = 26;
if (dnlp_alg_function != NULL) {
dnlp_alg_function->dnlp_para_set(&dnlp_alg_output,
@@ -500,6 +554,34 @@ void ve_set_v3_dnlp(struct ve_dnlp_curve_param_s *p)
/* general settings */
if (dnlp_insmod_ok == 0)
return;
/*load static curve*/
memcpy(dnlp_scurv_low_copy, p->ve_dnlp_scurv_low,
sizeof(int) * DNLP_SCURV_LEN);
memcpy(dnlp_scurv_mid1_copy, p->ve_dnlp_scurv_mid1,
sizeof(int) * DNLP_SCURV_LEN);
memcpy(dnlp_scurv_mid2_copy, p->ve_dnlp_scurv_mid2,
sizeof(int) * DNLP_SCURV_LEN);
memcpy(dnlp_scurv_hgh1_copy, p->ve_dnlp_scurv_hgh1,
sizeof(int) * DNLP_SCURV_LEN);
memcpy(dnlp_scurv_hgh2_copy, p->ve_dnlp_scurv_hgh2,
sizeof(int) * DNLP_SCURV_LEN);
/*load gain var*/
memcpy(gain_var_lut49_copy, p->ve_gain_var_lut49,
sizeof(int) * GAIN_VAR_LUT_LEN);
/*load wext gain*/
memcpy(wext_gain_copy, p->ve_wext_gain,
sizeof(int) * WEXT_GAIN_LEN);
/*load new c curve lut for vlsi-kite.li*/
memcpy(adp_thrd_copy, p->ve_adp_thrd,
sizeof(int) * ADP_THRD_LEN);
memcpy(reg_blk_boost_12_copy, p->ve_reg_blk_boost_12,
sizeof(int) * REG_BLK_BOOST_LEN);
memcpy(reg_adp_ofset_20_copy, p->ve_reg_adp_ofset_20,
sizeof(int) * REG_ADP_OFSET_LEN);
memcpy(reg_mono_protect_copy, p->ve_reg_mono_protect,
sizeof(int) * REG_MONO_PROT_LEN);
memcpy(reg_trend_wht_expand_lut8_copy, p->ve_reg_trend_wht_expand_lut8,
sizeof(int) * TREND_WHT_EXP_LUT_LEN);
if ((ve_en != p->param[ve_dnlp_enable]) ||
(dnlp_sel != p->param[ve_dnlp_sel]) ||
@@ -580,7 +662,45 @@ void ve_set_v3_dnlp(struct ve_dnlp_curve_param_s *p)
(dnlp_alg_param.dnlp_scurv_hgh2_th !=
p->param[ve_dnlp_scurv_hgh2_th]) ||
(dnlp_alg_param.dnlp_mtdrate_adp_en !=
p->param[ve_dnlp_mtdrate_adp_en])) {
p->param[ve_dnlp_mtdrate_adp_en]) ||
(dnlp_alg_param.dnlp_clahe_method !=
p->param[ve_dnlp_clahe_method]) ||
(dnlp_alg_param.dnlp_ble_en !=
p->param[ve_dnlp_ble_en]) ||
(dnlp_alg_param.dnlp_norm !=
p->param[ve_dnlp_norm]) ||
(dnlp_alg_param.dnlp_scn_chg_th !=
p->param[ve_dnlp_scn_chg_th]) ||
(dnlp_alg_param.dnlp_iir_step_mux !=
p->param[ve_dnlp_iir_step_mux]) ||
(dnlp_alg_param.dnlp_single_bin_bw !=
p->param[ve_dnlp_single_bin_bw]) ||
(dnlp_alg_param.dnlp_single_bin_method !=
p->param[ve_dnlp_single_bin_method]) ||
(dnlp_alg_param.dnlp_reg_max_slop_1st !=
p->param[ve_dnlp_reg_max_slop_1st]) ||
(dnlp_alg_param.dnlp_reg_max_slop_mid !=
p->param[ve_dnlp_reg_max_slop_mid]) ||
(dnlp_alg_param.dnlp_reg_max_slop_fin !=
p->param[ve_dnlp_reg_max_slop_fin]) ||
(dnlp_alg_param.dnlp_reg_min_slop_1st !=
p->param[ve_dnlp_reg_min_slop_1st]) ||
(dnlp_alg_param.dnlp_reg_min_slop_mid !=
p->param[ve_dnlp_reg_min_slop_mid]) ||
(dnlp_alg_param.dnlp_reg_min_slop_fin !=
p->param[ve_dnlp_reg_min_slop_fin]) ||
(dnlp_alg_param.dnlp_reg_trend_wht_expand_mode !=
p->param[ve_dnlp_reg_trend_wht_expand_mode]) ||
(dnlp_alg_param.dnlp_reg_trend_blk_expand_mode !=
p->param[ve_dnlp_reg_trend_blk_expand_mode]) ||
(dnlp_alg_param.dnlp_ve_hist_cur_gain !=
p->param[ve_dnlp_ve_hist_cur_gain]) ||
(dnlp_alg_param.dnlp_ve_hist_cur_gain_precise !=
p->param[ve_dnlp_ve_hist_cur_gain_precise]) ||
(dnlp_alg_param.dnlp_reg_mono_binrang_st !=
p->param[ve_dnlp_reg_mono_binrang_st]) ||
(dnlp_alg_param.dnlp_reg_mono_binrang_ed !=
p->param[ve_dnlp_reg_mono_binrang_ed])) {
if (dnlp_insmod_ok)
*menu_chg_en_copy = 1;
} else
@@ -651,27 +771,54 @@ void ve_set_v3_dnlp(struct ve_dnlp_curve_param_s *p)
dnlp_alg_param.dnlp_mtdrate_adp_en =
p->param[ve_dnlp_mtdrate_adp_en];
/* TODO: ve_dnlp_set_saturtn = p->dnlp_set_saturtn; */
/*new c curve param add for vlsi-kiteli*/
dnlp_alg_param.dnlp_mtdrate_adp_en =
p->param[ve_dnlp_mtdrate_adp_en];
dnlp_alg_param.dnlp_clahe_method =
p->param[ve_dnlp_clahe_method];
dnlp_alg_param.dnlp_ble_en =
p->param[ve_dnlp_ble_en];
dnlp_alg_param.dnlp_norm =
p->param[ve_dnlp_norm];
dnlp_alg_param.dnlp_scn_chg_th =
p->param[ve_dnlp_scn_chg_th];
dnlp_alg_param.dnlp_iir_step_mux =
p->param[ve_dnlp_iir_step_mux];
dnlp_alg_param.dnlp_single_bin_bw =
p->param[ve_dnlp_single_bin_bw];
dnlp_alg_param.dnlp_single_bin_method =
p->param[ve_dnlp_single_bin_method];
dnlp_alg_param.dnlp_reg_max_slop_1st =
p->param[ve_dnlp_reg_max_slop_1st];
dnlp_alg_param.dnlp_reg_max_slop_mid =
p->param[ve_dnlp_reg_max_slop_mid];
dnlp_alg_param.dnlp_reg_max_slop_fin =
p->param[ve_dnlp_reg_max_slop_fin];
dnlp_alg_param.dnlp_reg_min_slop_1st =
p->param[ve_dnlp_reg_min_slop_1st];
dnlp_alg_param.dnlp_reg_min_slop_mid =
p->param[ve_dnlp_reg_min_slop_mid];
dnlp_alg_param.dnlp_reg_min_slop_fin =
p->param[ve_dnlp_reg_min_slop_fin];
dnlp_alg_param.dnlp_reg_trend_wht_expand_mode =
p->param[ve_dnlp_reg_trend_wht_expand_mode];
dnlp_alg_param.dnlp_reg_trend_blk_expand_mode =
p->param[ve_dnlp_reg_trend_blk_expand_mode];
dnlp_alg_param.dnlp_ve_hist_cur_gain =
p->param[ve_dnlp_ve_hist_cur_gain];
dnlp_alg_param.dnlp_ve_hist_cur_gain_precise =
p->param[ve_dnlp_ve_hist_cur_gain_precise];
dnlp_alg_param.dnlp_reg_mono_binrang_st =
p->param[ve_dnlp_reg_mono_binrang_st];
dnlp_alg_param.dnlp_reg_mono_binrang_ed =
p->param[ve_dnlp_reg_mono_binrang_ed];
if (dnlp_insmod_ok == 0)
return;
dnlp_dbg_node_copy();
/*load static curve*/
for (i = 0; i < 65; i++) {
dnlp_scurv_low_copy[i] = p->ve_dnlp_scurv_low[i];
dnlp_scurv_mid1_copy[i] = p->ve_dnlp_scurv_mid1[i];
dnlp_scurv_mid2_copy[i] = p->ve_dnlp_scurv_mid2[i];
dnlp_scurv_hgh1_copy[i] = p->ve_dnlp_scurv_hgh1[i];
dnlp_scurv_hgh2_copy[i] = p->ve_dnlp_scurv_hgh2[i];
}
/*load gain var*/
for (i = 0; i < 49; i++)
gain_var_lut49_copy[i] = p->ve_gain_var_lut49[i];
/*load wext gain*/
for (i = 0; i < 48; i++)
wext_gain_copy[i] = p->ve_wext_gain[i];
if (ve_en) {
/* clear historic luma sum */
*ve_dnlp_luma_sum_copy = 0;

25
drivers/amlogic/media/enhancement/amvecm/dnlp_cal.h
View File

@@ -76,6 +76,26 @@ struct dnlp_alg_param_s {
unsigned int dnlp_scurv_hgh1_th;
unsigned int dnlp_scurv_hgh2_th;
unsigned int dnlp_mtdrate_adp_en;
unsigned int dnlp_clahe_method;
unsigned int dnlp_ble_en;
unsigned int dnlp_norm;
unsigned int dnlp_scn_chg_th;
unsigned int dnlp_step_th;
unsigned int dnlp_iir_step_mux;
unsigned int dnlp_single_bin_bw;
unsigned int dnlp_single_bin_method;
unsigned int dnlp_reg_max_slop_1st;
unsigned int dnlp_reg_max_slop_mid;
unsigned int dnlp_reg_max_slop_fin;
unsigned int dnlp_reg_min_slop_1st;
unsigned int dnlp_reg_min_slop_mid;
unsigned int dnlp_reg_min_slop_fin;
unsigned int dnlp_reg_trend_wht_expand_mode;
unsigned int dnlp_reg_trend_blk_expand_mode;
unsigned int dnlp_ve_hist_cur_gain;
unsigned int dnlp_ve_hist_cur_gain_precise;
unsigned int dnlp_reg_mono_binrang_st;
unsigned int dnlp_reg_mono_binrang_ed;
};
struct dnlp_parse_cmd_s {
@@ -108,6 +128,11 @@ extern int *dnlp_scurv_hgh1_copy;
extern int *dnlp_scurv_hgh2_copy;
extern int *gain_var_lut49_copy;
extern int *wext_gain_copy;
extern int *adp_thrd_copy;
extern int *reg_blk_boost_12_copy;
extern int *reg_adp_ofset_20_copy;
extern int *reg_mono_protect_copy;
extern int *reg_trend_wht_expand_lut8_copy;
extern int *ro_luma_avg4_copy;
extern int *ro_var_d8_copy;

58
include/linux/amlogic/media/amvecm/ve.h
View File

@@ -53,6 +53,16 @@ struct ve_bext_s {
unsigned char slope2;
};
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
#define DNLP_SCURV_LEN 65
#define GAIN_VAR_LUT_LEN 49
#define WEXT_GAIN_LEN 48
#define ADP_THRD_LEN 33
#define REG_BLK_BOOST_LEN 13
#define REG_ADP_OFSET_LEN 20
#define REG_MONO_PROT_LEN 6
#define TREND_WHT_EXP_LUT_LEN 9
#define DNLP_PARM_MAX_NUM 100
#define DNLP_VPP_HIST_BIN_NUM 64
struct ve_dnlp_s {
unsigned int en;
unsigned int rt; /* 0 ~ 255, */
@@ -71,17 +81,22 @@ struct vpp_hist_param_s {
unsigned int vpp_hist_pow;
unsigned int vpp_luma_sum;
unsigned int vpp_pixel_sum;
unsigned short vpp_histgram[64];
unsigned short vpp_histgram[DNLP_VPP_HIST_BIN_NUM];
};
struct ve_dnlp_curve_param_s {
unsigned int ve_dnlp_scurv_low[65];
unsigned int ve_dnlp_scurv_mid1[65];
unsigned int ve_dnlp_scurv_mid2[65];
unsigned int ve_dnlp_scurv_hgh1[65];
unsigned int ve_dnlp_scurv_hgh2[65];
unsigned int ve_gain_var_lut49[49];
unsigned int ve_wext_gain[48];
unsigned int param[100];
unsigned int ve_dnlp_scurv_low[DNLP_SCURV_LEN];
unsigned int ve_dnlp_scurv_mid1[DNLP_SCURV_LEN];
unsigned int ve_dnlp_scurv_mid2[DNLP_SCURV_LEN];
unsigned int ve_dnlp_scurv_hgh1[DNLP_SCURV_LEN];
unsigned int ve_dnlp_scurv_hgh2[DNLP_SCURV_LEN];
unsigned int ve_gain_var_lut49[GAIN_VAR_LUT_LEN];
unsigned int ve_wext_gain[WEXT_GAIN_LEN];
unsigned int ve_adp_thrd[ADP_THRD_LEN];
unsigned int ve_reg_blk_boost_12[REG_BLK_BOOST_LEN];
unsigned int ve_reg_adp_ofset_20[REG_ADP_OFSET_LEN];
unsigned int ve_reg_mono_protect[REG_MONO_PROT_LEN];
unsigned int ve_reg_trend_wht_expand_lut8[TREND_WHT_EXP_LUT_LEN];
unsigned int param[DNLP_PARM_MAX_NUM];
};
enum dnlp_param_e {
ve_dnlp_enable = 0,
@@ -141,6 +156,26 @@ enum dnlp_param_e {
ve_dnlp_scurv_hgh1_th,
ve_dnlp_scurv_hgh2_th,
ve_dnlp_mtdrate_adp_en,
ve_dnlp_clahe_method,
ve_dnlp_ble_en,
ve_dnlp_norm,
ve_dnlp_scn_chg_th,
ve_dnlp_step_th,
ve_dnlp_iir_step_mux,
ve_dnlp_single_bin_bw,
ve_dnlp_single_bin_method,
ve_dnlp_reg_max_slop_1st,
ve_dnlp_reg_max_slop_mid,
ve_dnlp_reg_max_slop_fin,
ve_dnlp_reg_min_slop_1st,
ve_dnlp_reg_min_slop_mid,
ve_dnlp_reg_min_slop_fin,
ve_dnlp_reg_trend_wht_expand_mode,
ve_dnlp_reg_trend_blk_expand_mode,
ve_dnlp_ve_hist_cur_gain,
ve_dnlp_ve_hist_cur_gain_precise,
ve_dnlp_reg_mono_binrang_st,
ve_dnlp_reg_mono_binrang_ed,
ve_dnlp_param_max,
};
enum dnlp_curve_e {
@@ -151,6 +186,11 @@ enum dnlp_curve_e {
ve_scurv_hgh2,
ve_curv_var_lut49,
ve_curv_wext_gain,
ve_adp_thrd = 1013,
ve_reg_blk_boost_12,
ve_reg_adp_ofset_20,
ve_reg_mono_protect,
ve_reg_trend_wht_expand_lut8,
};
#else
struct ve_dnlp_s {