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arm64: dts: rockchip: rk3568: set codec relative clock freq

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Change-Id: Icd3de01aeb6887add17966aa02515623a933e7ee
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei
2020-11-16 09:31:36 +08:00
committed by Tao Huang
parent d4cec57949
commit 06a91e1527
1 changed files with 13 additions and 9 deletions
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22
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -887,9 +887,7 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,normal-rates = <400000000>, <0>;
rockchip,advanced-rates = <500000000>, <0>;
rockchip,default-max-load = <2088960>;
rockchip,normal-rates = <297000000>, <0>;
resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
reset-names = "video_a", "video_h";
iommus = <&jpegd_mmu>;
@@ -918,9 +916,7 @@
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,normal-rates = <400000000>, <0>;
rockchip,advanced-rates = <500000000>, <0>;
rockchip,default-max-load = <2088960>;
rockchip,normal-rates = <297000000>, <0>;
resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>;
reset-names = "video_a", "video_h";
iommus = <&vepu_mmu>;
@@ -990,14 +986,14 @@
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
<&cru CLK_RKVENC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <300000000>, <0>, <400000000>;
rockchip,advanced-rates = <300000000>, <0>, <600000000>;
rockchip,normal-rates = <297000000>, <0>, <400000000>;
rockchip,advanced-rates = <297000000>, <0>, <500000000>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
<&cru SRST_RKVENC_CORE>;
reset-names = "video_a", "video_h", "video_core";
assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
assigned-clock-rates = <297000000>, <594000000>;
assigned-clock-rates = <297000000>, <297000000>;
iommus = <&rkvenc_mmu>;
node-name = "rkvenc";
rockchip,srv = <&mpp_srv>;
@@ -1032,9 +1028,17 @@
<&cru CLK_RKVDEC_HEVC_CA>;
clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac",
"clk_core", "clk_hevc_cabac";
rockchip,normal-rates = <297000000>, <0>, <297000000>,
<297000000>, <400000000>;
rockchip,advanced-rates = <400000000>, <0>, <400000000>,
<400000000>, <500000000>;
rockchip,default-max-load = <2088960>;
resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
<&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>,
<&cru SRST_RKVDEC_HEVC_CA>;
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>,
<&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>;
assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>;
reset-names = "video_a", "video_h", "video_cabac",
"video_core", "video_hevc_cabac";
power-domains = <&power RK3568_PD_RKVDEC>;