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media: rockchip: phy: Support for RK1808

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Change-Id: I02a27e9c829515fe16876fc228b2107e83603daf
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This commit is contained in:
Hu Kejun
2018-10-09 19:59:19 +08:00
committed by Tao Huang
parent c2c26aab99
commit 06ec79c3ad
1 changed files with 158 additions and 24 deletions
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182
drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
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@@ -46,6 +46,8 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
#define RK3288_GRF_SOC_CON6 0x025c
#define RK3288_GRF_SOC_CON8 0x0264
#define RK3288_GRF_SOC_CON9 0x0268
@@ -85,14 +87,40 @@
#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75
/* LOW POWER MODE SET */
#define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET 0x00
#define MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 0xFFFF
#define RK1808_CSI_DPHY_CTRL_LANE_ENABLE 0x00
#define RK1808_CSI_DPHY_CTRL_PWRCTL \
MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
#define RK1808_CSI_DPHY_CTRL_DIG_RST 0x80
#define RK3326_CSI_DPHY_CTRL_LANE_ENABLE 0x00
#define RK3326_CSI_DPHY_CTRL_PWRCTL 0x04
#define RK3326_CSI_DPHY_CTRL_DIG_RST 0x80
#define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
#define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
#define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET 0x04
#define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET 0x80
/* Configure the count time of the THS-SETTLE by protocol. */
#define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET 0x00
#define RK1808_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
#define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE \
(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
#define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE \
(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
#define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE \
(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
#define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE \
(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
#define RK3326_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
#define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE \
(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
#define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE \
(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
#define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE \
(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
#define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE \
(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
/*
* CSI HOST
@@ -106,12 +134,6 @@
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
/* csi phy */
#define write_csiphy_reg(addr, val) \
writel(val, addr + csihost_base_addr)
#define read_csiphy_reg(addr) \
readl(addr + csihost_base_addr)
enum mipi_dphy_sy_pads {
MIPI_DPHY_SY_PAD_SINK = 0,
MIPI_DPHY_SY_PAD_SOURCE,
@@ -147,7 +169,7 @@ enum dphy_reg_id {
GRF_CON_ISP_DPHY_SEL,
GRF_DSI_CSI_TESTBUS_SEL,
GRF_DVP_V18SEL,
/* rk3326 only */
/* rk1808 & rk3326 */
GRF_DPHY_CSIPHY_FORCERXMODE,
GRF_DPHY_CSIPHY_CLKLANE_EN,
GRF_DPHY_CSIPHY_DATALANE_EN,
@@ -157,6 +179,17 @@ enum dphy_reg_id {
GRF_DPHY_TX1RX1_SRC_SEL,
};
enum csiphy_reg_id {
CSIPHY_CTRL_LANE_ENABLE = 0,
CSIPHY_CTRL_PWRCTL,
CSIPHY_CTRL_DIG_RST,
CSIPHY_CLK_THS_SETTLE,
CSIPHY_LANE0_THS_SETTLE,
CSIPHY_LANE1_THS_SETTLE,
CSIPHY_LANE2_THS_SETTLE,
CSIPHY_LANE3_THS_SETTLE
};
enum mipi_dphy_ctl_type {
MIPI_DPHY_CTL_GRF_ONLY = 0,
MIPI_DPHY_CTL_CSI_HOST
@@ -187,12 +220,25 @@ struct txrx_reg {
u32 offset;
};
struct csiphy_reg {
u32 offset;
};
#define PHY_REG(_offset, _width, _shift) \
{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
#define TXRX_REG(_offset) \
{ .offset = _offset, }
#define CSIPHY_REG(_offset) \
{ .offset = _offset, }
static const struct dphy_reg rk1808_grf_dphy_regs[] = {
[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
};
static const struct dphy_reg rk3288_grf_dphy_regs[] = {
[GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
[GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
@@ -273,6 +319,28 @@ static const struct txrx_reg rk3399_txrx_regs[] = {
[TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ),
};
static const struct csiphy_reg rk1808_csiphy_regs[] = {
[CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_LANE_ENABLE),
[CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_PWRCTL),
[CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_DIG_RST),
[CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE),
[CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE),
[CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE),
[CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE),
[CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE),
};
static const struct csiphy_reg rk3326_csiphy_regs[] = {
[CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
[CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
[CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
[CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE),
[CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE),
[CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE),
[CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE),
[CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE),
};
struct hsfreq_range {
u32 range_h;
u8 cfg_bit;
@@ -287,6 +355,7 @@ struct dphy_drv_data {
int num_hsfreq_ranges;
const struct dphy_reg *grf_regs;
const struct txrx_reg *txrx_regs;
const struct csiphy_reg *csiphy_regs;
enum mipi_dphy_ctl_type ctl_type;
void (*individual_init)(struct mipidphy_priv *priv);
};
@@ -311,6 +380,7 @@ struct mipidphy_priv {
struct regmap *regmap_grf;
const struct dphy_reg *grf_regs;
const struct txrx_reg *txrx_regs;
const struct csiphy_reg *csiphy_regs;
void __iomem *csihost_base_addr;
struct clk *clks[MAX_DPHY_CLK];
const struct dphy_drv_data *drv_data;
@@ -381,16 +451,53 @@ static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02);
}
static inline void write_csiphy_reg(struct mipidphy_priv *priv,
int index, u32 value)
{
const struct csiphy_reg *reg = &priv->csiphy_regs[index];
if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
writel(value, priv->csihost_base_addr + reg->offset);
}
static inline void read_csiphy_reg(struct mipidphy_priv *priv,
int index, u32 *value)
{
const struct csiphy_reg *reg = &priv->csiphy_regs[index];
if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
*value = readl(priv->csihost_base_addr + reg->offset);
}
static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq,
enum mipi_dphy_lane lane)
{
unsigned int val;
unsigned int offset = 0x100 + 0x80 * lane;
void __iomem *csihost_base_addr = priv->csihost_base_addr;
unsigned int val = 0;
unsigned int offset;
val = hsfreq;
val |= read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + offset) & (~0xf);
write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + offset), val);
switch (lane) {
case MIPI_DPHY_LANE_CLOCK:
offset = CSIPHY_CLK_THS_SETTLE;
break;
case MIPI_DPHY_LANE_DATA0:
offset = CSIPHY_LANE0_THS_SETTLE;
break;
case MIPI_DPHY_LANE_DATA1:
offset = CSIPHY_LANE1_THS_SETTLE;
break;
case MIPI_DPHY_LANE_DATA2:
offset = CSIPHY_LANE2_THS_SETTLE;
break;
case MIPI_DPHY_LANE_DATA3:
offset = CSIPHY_LANE3_THS_SETTLE;
break;
default:
return;
}
read_csiphy_reg(priv, offset, &val);
val = (val & ~0xf) | hsfreq;
write_csiphy_reg(priv, offset, val);
}
static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
@@ -586,6 +693,14 @@ static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
};
/* These tables must be sorted by .range_h ascending. */
static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = {
{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
{1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
{2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
};
static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
{ 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
{ 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
@@ -617,6 +732,10 @@ static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
{1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
};
static const char * const rk1808_mipidphy_clks[] = {
"pclk",
};
static const char * const rk3288_mipidphy_clks[] = {
"dphy-ref",
"pclk",
@@ -855,25 +974,24 @@ static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
int i, hsfreq = 0;
void __iomem *csihost_base_addr = priv->csihost_base_addr;
write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
/* phy start */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);
/* set data lane num and enable clock lane */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET,
write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,
((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
(0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1));
/* Reset dphy analog part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);
usleep_range(500, 1000);
/* Reset dphy digital part */
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
/* not into receive mode/wait stopstate */
write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
@@ -902,6 +1020,17 @@ static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
return 0;
}
static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
.clks = rk1808_mipidphy_clks,
.num_clks = ARRAY_SIZE(rk1808_mipidphy_clks),
.hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
.num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
.grf_regs = rk1808_grf_dphy_regs,
.csiphy_regs = rk1808_csiphy_regs,
.ctl_type = MIPI_DPHY_CTL_CSI_HOST,
.individual_init = default_mipidphy_individual_init,
};
static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
.clks = rk3288_mipidphy_clks,
.num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
@@ -911,7 +1040,6 @@ static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
.txrx_regs = rk3288_txrx_regs,
.ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
.individual_init = default_mipidphy_individual_init,
};
static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
@@ -920,6 +1048,7 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
.hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
.num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
.grf_regs = rk3326_grf_dphy_regs,
.csiphy_regs = rk3326_csiphy_regs,
.ctl_type = MIPI_DPHY_CTL_CSI_HOST,
.individual_init = default_mipidphy_individual_init,
};
@@ -936,6 +1065,10 @@ static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
};
static const struct of_device_id rockchip_mipidphy_match_id[] = {
{
.compatible = "rockchip,rk1808-mipi-dphy-rx",
.data = &rk1808_mipidphy_drv_data,
},
{
.compatible = "rockchip,rk3288-mipi-dphy",
.data = &rk3288_mipidphy_drv_data,
@@ -1141,6 +1274,7 @@ static int rockchip_mipidphy_probe(struct platform_device *pdev)
priv->grf_regs = drv_data->grf_regs;
priv->txrx_regs = drv_data->txrx_regs;
priv->csiphy_regs = drv_data->csiphy_regs;
priv->drv_data = drv_data;
if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);