mirror of
https://github.com/hardkernel/linux.git
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Merge commit '9fdcd51c80f1aa6f80c188979609a429fe4fb422'
* commit '9fdcd51c80f1aa6f80c188979609a429fe4fb422': input: sensors: accel: mxc6655xa: add missing sync events. dmaengine: pl330: Optimize scatterlist transfer dmaengine: pl330: Add support SRC_INC/DST_INC for interleaved PCI: rockchip: dw: Extract out rk_pcie_host_config() drm/rockchip: dw_hdmi: Restore hpd elimination buffeting time to 150ms arm64: dts: rockchip: rk3576-vehicle-evb: init v20 dts files media: i2c: rk628: cancel audio work when hdmirx reset ASoC: rockchip: multicodecs: Correct error code for tdm slot configuration arm64: dts: rockchip: rk3326-evb-lp3-v10: Add vbus-supply for usb2 otg Change-Id: I60ca21a0a5b144be8b3c2e6390c2610b861b5e0b
This commit is contained in:
Tao Huang
@@ -274,6 +274,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test3-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-test5-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-vehicle-evb-v20-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dtb
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@@ -826,6 +826,7 @@
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};
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&usb20_otg {
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vbus-supply = <&otg_switch>;
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status = "okay";
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};
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522
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-linux.dts
Normal file
522
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-linux.dts
Normal file
@@ -0,0 +1,522 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3576.dtsi"
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#include "rk3576-vehicle-evb-v20.dtsi"
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#include "rk3576-vehicle-evb-v20-nca9539-io-expander.dtsi"
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#include "rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi"
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#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy0-isx021.dtsi"
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#include "rk3576-linux.dtsi"
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/ {
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model = "Rockchip RK3576 VEHICLE EVB V20 Board";
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compatible = "rockchip,rk3576-vehicle-evb-v20", "rockchip,rk3576";
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vehicle_dummy: vehicle-dummy {
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status = "okay";
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compatible = "rockchip,vehicle-dummy-adc";
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io-channels = <&saradc 4>, <&saradc 5>, <&saradc 6>;
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io-channel-names = "gear", "turn_left", "turn_right";
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};
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vcc5v0_buck: vcc5v0-buck {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc12v_dcin>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_buck_en>;
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startup-delay-us = <2500>;
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off-on-delay-us = <1500>;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <5000000>;
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};
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};
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cluster_power_buck: cluster_power-buck {
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compatible = "regulator-fixed";
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regulator-name = "cluster_power_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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//enable-active-high;
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gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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vin-supply = <&vcc_1v8_s0>;
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pinctrl-names = "default";
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pinctrl-0 = <&cluster_buck_en>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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usb_otg0_vcc5v_buck: usb_otg0_vcc5v-buck {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg0_vcc5v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_buck>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <5000000>;
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};
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};
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usb_host_vcc5v_buck: usb_host_vcc5v-buck {
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compatible = "regulator-fixed";
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regulator-name = "usb_host_vcc5v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_buck>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <5000000>;
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};
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};
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lcd1_vcc12v_buck: lcd1_vcc12v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd1_vcc12v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc12v_dcin>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <12000000>;
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};
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};
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lcd2_vcc12v_buck: lcd2_vcc12v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd2_vcc12v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc12v_dcin>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <12000000>;
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};
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};
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lcd1_ser_vcc5v_buck: lcd1_ser_vcc5v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd1_ser_vcc5v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_buck>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <5000000>;
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};
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};
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lcd2_ser_vcc5v_buck: lcd2_ser_vcc5v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd2_ser_vcc5v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_buck>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <5000000>;
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};
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};
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adsp_vcc12v_buck: adsp_vcc12v-buck {
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compatible = "regulator-fixed";
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regulator-name = "adsp_vcc12v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&i2c0_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc12v_dcin>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <12000000>;
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};
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};
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lcd3_vcc12v_buck: lcd3_vcc12v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd3_vcc12v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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gpio = <&i2c7_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc12v_dcin>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <12000000>;
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};
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};
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lcd3_vcc5v_buck: lcd3_vcc5v-buck {
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compatible = "regulator-fixed";
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regulator-name = "lcd3_vcc5v_buck";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&i2c7_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
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regulator-state-mem {
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regulator-off-in-suspend;
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regulator-suspend-microvolt = <12000000>;
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};
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};
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dcphy0_vcc12v_buck1: dcphy0_vcc12v-buck1 {
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compatible = "regulator-fixed";
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regulator-name = "dcphy0_vcc12v_buck1";
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regulator-boot-on;
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||||
regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
|
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enable-active-high;
|
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gpio = <&i2c7_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
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||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
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regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
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regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
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|
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dcphy0_vcc12v_buck2: dcphy0_vcc12v-buck2 {
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compatible = "regulator-fixed";
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regulator-name = "dcphy0_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck3: dcphy0_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck4: dcphy0_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck1: dphy0_vcc12v-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck2: dphy0_vcc12v-buck2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck3: dphy0_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck4: dphy0_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck1: dphy3_vcc12v-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck2: dphy3_vcc12v-buck2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck3: dphy3_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck4: dphy3_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&hym8563 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*edp*/
|
||||
&i2c3_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd1_vcc12v_buck>;
|
||||
};
|
||||
|
||||
/*edp touch*/
|
||||
&i2c3_himax {
|
||||
himax,irq-gpio = <&gpio3 RK_PD6 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
/*dp*/
|
||||
&i2c5_max96745 {
|
||||
lock-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c5_ilitek {
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/*dp*/
|
||||
&i2c5_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd2_vcc12v_buck>;
|
||||
};
|
||||
|
||||
/*dsi*/
|
||||
&i2c8_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd3_vcc12v_buck>;
|
||||
};
|
||||
|
||||
&dp2lvds_backlight0 {
|
||||
pwms = <&pwm2_8ch_7 0 25000 0>;
|
||||
};
|
||||
|
||||
&edp2lvds_backlight0 {
|
||||
pwms = <&pwm0_2ch_0 0 25000 0>;
|
||||
};
|
||||
|
||||
/* edp->serdes->lvds_panel */
|
||||
&pwm0_2ch_0 {
|
||||
pinctrl-0 = <&pwm0m3_ch0>;
|
||||
};
|
||||
|
||||
/* dp->serdes->lvds_panel */
|
||||
&pwm2_8ch_7 {
|
||||
pinctrl-0 = <&pwm2m3_ch7>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
touch {
|
||||
//dsi-i2c8
|
||||
touch_gpio_dsi: touch-gpio-dsi {
|
||||
rockchip,pins =
|
||||
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
//dp-i2c5
|
||||
touch_gpio_dp: touch-gpio-dp {
|
||||
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
//edp0-i2c3
|
||||
touch_gpio_edp: touch-gpio-edp {
|
||||
rockchip,pins =
|
||||
<3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0-buck {
|
||||
vcc5v0_buck_en: vcc5v0-buck-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster-buck {
|
||||
cluster_buck_en: cluster-buck-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkvpss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvpss_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvpss_vir0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -0,0 +1,725 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
|
||||
/ {
|
||||
max96712_dphy0_osc: max96712-dphy0-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "max96712-dphy0-osc";
|
||||
};
|
||||
|
||||
max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_vcc1v2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
startup-delay-us = <850>;
|
||||
vin-supply = <&vcc_2v0_pldo_s3>;
|
||||
};
|
||||
|
||||
max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_vcc1v8";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
startup-delay-us = <200>;
|
||||
vin-supply = <&vcc_2v0_pldo_s3>;
|
||||
};
|
||||
|
||||
max96712_dphy0_pwdn_regulator: max96712-dphy0-pwdn-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_pwdn";
|
||||
gpio = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max96712_dphy0_pwdn>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <10000>;
|
||||
off-on-delay-us = <5000>;
|
||||
};
|
||||
|
||||
max96712_dphy0_poc_regulator: max96712-dphy0-poc0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_poc";
|
||||
gpio = <&i2c7_nca9539_gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <10000>;
|
||||
off-on-delay-us = <5000>;
|
||||
vin-supply = <&dphy0_vcc12v_buck1>;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_dphy0_in_max96712: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&max96712_dphy0_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi1_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m1_xfer>;
|
||||
|
||||
max96712_dphy0: max96712@29 {
|
||||
compatible = "maxim4c,max96712";
|
||||
status = "okay";
|
||||
reg = <0x29>;
|
||||
clock-names = "xvclk";
|
||||
clocks = <&max96712_dphy0_osc 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max96712_dphy0_errb>, <&max96712_dphy0_lock>;
|
||||
power-domains = <&power RK3576_PD_VI>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
vcc1v2-supply = <&max96712_dphy0_vcc1v2>;
|
||||
vcc1v8-supply = <&max96712_dphy0_vcc1v8>;
|
||||
pwdn-supply = <&max96712_dphy0_pwdn_regulator>;
|
||||
lock-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
port {
|
||||
max96712_dphy0_out: endpoint {
|
||||
remote-endpoint = <&mipi_dphy0_in_max96712>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
/* support mode config start */
|
||||
support-mode-config {
|
||||
status = "okay";
|
||||
|
||||
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
|
||||
sensor-width = <1920>;
|
||||
sensor-height = <1281>;
|
||||
crop-rect = <0 1 1920 1280>; // [ left, top, width, height ]
|
||||
max-fps-numerator = <10000>;
|
||||
max-fps-denominator = <300000>;
|
||||
bpp = <16>;
|
||||
link-freq-idx = <20>;
|
||||
};
|
||||
/* support mode config end */
|
||||
|
||||
/* serdes local device start */
|
||||
serdes-local-device {
|
||||
status = "okay";
|
||||
|
||||
/* GMSL LINK config start */
|
||||
gmsl-links {
|
||||
status = "okay";
|
||||
|
||||
link-vdd-ldo1-en = <1>;
|
||||
link-vdd-ldo2-en = <1>;
|
||||
|
||||
// Link A: link-id = 0
|
||||
gmsl-link-config-0 {
|
||||
status = "okay";
|
||||
link-id = <0>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam0>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
14 D1 03 00 00 // VGAHiGain
|
||||
14 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link B: link-id = 1
|
||||
gmsl-link-config-1 {
|
||||
status = "okay";
|
||||
link-id = <1>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam1>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
15 D1 03 00 00 // VGAHiGain
|
||||
15 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link C: link-id = 2
|
||||
gmsl-link-config-2 {
|
||||
status = "okay";
|
||||
link-id = <2>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam2>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
16 D1 03 00 00 // VGAHiGain
|
||||
16 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link D: link-id = 3
|
||||
gmsl-link-config-3 {
|
||||
status = "okay";
|
||||
link-id = <3>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <0>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam3>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
17 D1 03 00 00 // VGAHiGain
|
||||
17 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
/* GMSL LINK config end */
|
||||
|
||||
/* VIDEO PIPE config start */
|
||||
video-pipes {
|
||||
status = "okay";
|
||||
|
||||
// Video Pipe 0
|
||||
video-pipe-config-0 {
|
||||
status = "okay";
|
||||
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
|
||||
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
|
||||
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
|
||||
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 1
|
||||
video-pipe-config-1 {
|
||||
status = "okay";
|
||||
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
|
||||
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
|
||||
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
|
||||
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 2
|
||||
video-pipe-config-2 {
|
||||
status = "okay";
|
||||
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
|
||||
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
|
||||
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
|
||||
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 3
|
||||
video-pipe-config-3 {
|
||||
status = "okay";
|
||||
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
|
||||
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
|
||||
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
|
||||
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
/* VIDEO PIPE config end */
|
||||
|
||||
/* MIPI TXPHY config start */
|
||||
mipi-txphys {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
|
||||
phy-force-clock-out = <1>; // 1: default for force clock out
|
||||
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
|
||||
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
|
||||
|
||||
// MIPI TXPHY A: phy-id = 0
|
||||
mipi-txphy-config-0 {
|
||||
status = "okay";
|
||||
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0x4>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
|
||||
// MIPI TXPHY B: phy-id = 1
|
||||
mipi-txphy-config-1 {
|
||||
status = "okay";
|
||||
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0xe>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
};
|
||||
/* MIPI TXPHY config end */
|
||||
|
||||
/* local device extra init sequence */
|
||||
extra-init-sequence {
|
||||
status = "okay";
|
||||
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// common init sequence such as fsync / gpio and so on
|
||||
04 A2 00 00 00 // Master link Video 0 for frame sync generation
|
||||
04 AA 00 00 00 // Disable Vsync-Fsync overlap window
|
||||
04 AB 00 00 00 // Disable Vsync-Fsync overlap window
|
||||
04 A8 00 00 00 // FRM_DIFF_ERR_THR_L
|
||||
04 A9 00 00 00 // FRM_DIFF_ERR_THR_H
|
||||
04 A7 0c 00 00 // FSYNC_PERIOD_H, Set FSYNC period to 25M/30 clock cycles. PCLK = 25MHz. Sync freq = 30Hz
|
||||
04 A6 bf 00 00 // FSYNC_PERIOD_M
|
||||
04 A5 35 00 00 // FSYNC_PERIOD_L
|
||||
04 AF c0 00 00 // FSYNC is GMSL2 type, use osc for fsync
|
||||
04 B1 40 00 00 // FSYNC_TX_ID: set 8 to match MFP8 on serializer side
|
||||
04 A0 04 00 00 // MFP2, VS not gen internally, GPIO not used to gen fsync, manual mode
|
||||
];
|
||||
};
|
||||
};
|
||||
/* serdes local device end */
|
||||
|
||||
/* i2c-mux start */
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser0: max96717@51 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x51>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam0: isx021@31 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x31>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser0>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam0_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser1: max96717@52 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x52>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam1: isx021@32 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x32>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser1>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam1_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser2: max96717@53 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x53>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam2: isx021@33 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x33>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser2>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <2>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam2_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser3: max96717@54 {
|
||||
compatible = "maxim,ser,max96717f";
|
||||
reg = <0x54>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam3: isx021@34 {
|
||||
compatible = "maxim,dummy,sensor";
|
||||
reg = <0x34>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser3>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <3>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam3_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
};
|
||||
/* i2c-mux end */
|
||||
};
|
||||
};
|
||||
|
||||
&mipi1_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi1_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi1_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds1 {
|
||||
status = "okay";
|
||||
/* parameters for do cif reset detecting:
|
||||
* index0: monitor mode,
|
||||
0 for idle,
|
||||
1 for continue,
|
||||
2 for trigger,
|
||||
3 for hotplug (for nextchip)
|
||||
* index1: the frame id to start timer,
|
||||
min is 2
|
||||
* index2: frame num of monitoring cycle
|
||||
* index3: err time for keep monitoring
|
||||
after finding out err (ms)
|
||||
* index4: csi2 err reference val for resetting
|
||||
*/
|
||||
rockchip,cif-monitor = <3 2 1 1000 5>;
|
||||
|
||||
port {
|
||||
cif_mipi1_in: endpoint {
|
||||
remote-endpoint = <&mipi1_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
rockchip,android-usb-camerahal-enable;
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
max96712-dphy0 {
|
||||
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
|
||||
rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
max96712_dphy0_errb: max96712-dphy0-errb {
|
||||
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
max96712_dphy0_lock: max96712-dphy0-lock {
|
||||
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,713 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#include <dt-bindings/display/media-bus-format.h>
|
||||
|
||||
/ {
|
||||
max96712_dphy0_osc: max96712-dphy0-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "max96712-dphy0-osc";
|
||||
};
|
||||
|
||||
max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_vcc1v2";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
startup-delay-us = <850>;
|
||||
vin-supply = <&vcc_2v0_pldo_s3>;
|
||||
};
|
||||
|
||||
max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_vcc1v8";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
startup-delay-us = <200>;
|
||||
vin-supply = <&vcc_2v0_pldo_s3>;
|
||||
};
|
||||
|
||||
max96712_dphy0_pwdn_regulator: max96712-dphy0-pwdn-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_pwdn";
|
||||
gpio = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max96712_dphy0_pwdn>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <10000>;
|
||||
off-on-delay-us = <5000>;
|
||||
};
|
||||
|
||||
max96712_dphy0_poc_regulator: max96712-dphy0-poc0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "max96712_dphy0_poc";
|
||||
gpio = <&i2c7_nca9539_gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <10000>;
|
||||
off-on-delay-us = <5000>;
|
||||
vin-supply = <&dphy0_vcc12v_buck1>;
|
||||
};
|
||||
};
|
||||
|
||||
&csi2_dphy0_hw {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi_dphy0_in_max96712: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&max96712_dphy0_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi1_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m1_xfer>;
|
||||
|
||||
max96712_dphy0: max96712@29 {
|
||||
compatible = "maxim4c,max96712";
|
||||
status = "okay";
|
||||
reg = <0x29>;
|
||||
clock-names = "xvclk";
|
||||
clocks = <&max96712_dphy0_osc 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max96712_dphy0_errb>, <&max96712_dphy0_lock>;
|
||||
power-domains = <&power RK3576_PD_VI>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
vcc1v2-supply = <&max96712_dphy0_vcc1v2>;
|
||||
vcc1v8-supply = <&max96712_dphy0_vcc1v8>;
|
||||
pwdn-supply = <&max96712_dphy0_pwdn_regulator>;
|
||||
lock-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
port {
|
||||
max96712_dphy0_out: endpoint {
|
||||
remote-endpoint = <&mipi_dphy0_in_max96712>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
/* support mode config start */
|
||||
support-mode-config {
|
||||
status = "okay";
|
||||
|
||||
bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
|
||||
sensor-width = <1920>;
|
||||
sensor-height = <1440>;
|
||||
max-fps-numerator = <10000>;
|
||||
max-fps-denominator = <300000>;
|
||||
bpp = <16>;
|
||||
link-freq-idx = <20>;
|
||||
};
|
||||
/* support mode config end */
|
||||
|
||||
/* serdes local device start */
|
||||
serdes-local-device {
|
||||
status = "okay";
|
||||
|
||||
/* GMSL LINK config start */
|
||||
gmsl-links {
|
||||
status = "okay";
|
||||
|
||||
link-vdd-ldo1-en = <1>;
|
||||
link-vdd-ldo2-en = <1>;
|
||||
|
||||
// Link A: link-id = 0
|
||||
gmsl-link-config-0 {
|
||||
status = "okay";
|
||||
link-id = <0>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam0>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
14 D1 03 00 00 // VGAHiGain
|
||||
14 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link B: link-id = 1
|
||||
gmsl-link-config-1 {
|
||||
status = "okay";
|
||||
link-id = <1>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam1>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
15 D1 03 00 00 // VGAHiGain
|
||||
15 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link C: link-id = 2
|
||||
gmsl-link-config-2 {
|
||||
status = "okay";
|
||||
link-id = <2>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam2>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
16 D1 03 00 00 // VGAHiGain
|
||||
16 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Link D: link-id = 3
|
||||
gmsl-link-config-3 {
|
||||
status = "okay";
|
||||
link-id = <3>; // Link ID: 0/1/2/3
|
||||
|
||||
link-type = <1>; // 0: GMSL1, 1: GMSL2
|
||||
link-rx-rate = <1>; // 0: 3GBPS, 1: 6GBPS
|
||||
link-tx-rate = <0>; // 0: default for 187.5MBPS
|
||||
|
||||
link-remote-cam = <&max96712_dphy0_cam3>; // remote camera
|
||||
|
||||
link-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
17 D1 03 00 00 // VGAHiGain
|
||||
17 45 00 00 00 // Disable SSC
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
/* GMSL LINK config end */
|
||||
|
||||
/* VIDEO PIPE config start */
|
||||
video-pipes {
|
||||
status = "okay";
|
||||
|
||||
// Video Pipe 0
|
||||
video-pipe-config-0 {
|
||||
status = "okay";
|
||||
pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <0>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
|
||||
09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
|
||||
09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
|
||||
09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 12 01 00 00 // DST2 VC = 0, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 1
|
||||
video-pipe-config-1 {
|
||||
status = "okay";
|
||||
pipe-id = <1>; // Video Pipe 1: pipe-id = 1
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <1>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
|
||||
09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
|
||||
09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
|
||||
09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 52 41 00 00 // DST2 VC = 1, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 2
|
||||
video-pipe-config-2 {
|
||||
status = "okay";
|
||||
pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <2>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 2 to Controller 1
|
||||
09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit
|
||||
09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 90 80 00 00 // DST1 VC = 2, DT = Frame Start
|
||||
09 91 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 92 81 00 00 // DST2 VC = 2, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
// Video Pipe 3
|
||||
video-pipe-config-3 {
|
||||
status = "okay";
|
||||
pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7
|
||||
|
||||
pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3
|
||||
link-idx = <3>; // Link A/B/C/D: 0/1/2/3
|
||||
|
||||
pipe-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// Send YUV422, FS, and FE from Video Pipe 3 to Controller 1
|
||||
09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings
|
||||
09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
|
||||
// For the following MSB 2 bits = VC, LSB 6 bits = DT
|
||||
09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
|
||||
09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit
|
||||
09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start
|
||||
09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start
|
||||
09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End
|
||||
09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End
|
||||
];
|
||||
};
|
||||
};
|
||||
};
|
||||
/* VIDEO PIPE config end */
|
||||
|
||||
/* MIPI TXPHY config start */
|
||||
mipi-txphys {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = <0>; // 0: 4Lanes, 1: 2Lanes
|
||||
phy-force-clock-out = <1>; // 1: default for force clock out
|
||||
phy-force-clk0-en = <1>; // provide MIPI clock: 0 = PHY1, 1 = PHY0
|
||||
phy-force-clk3-en = <0>; // provide MIPI clock: 0 = PHY2, 1 = PHY3
|
||||
|
||||
// MIPI TXPHY A: phy-id = 0
|
||||
mipi-txphy-config-0 {
|
||||
status = "okay";
|
||||
phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0x4>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
|
||||
// MIPI TXPHY B: phy-id = 1
|
||||
mipi-txphy-config-1 {
|
||||
status = "okay";
|
||||
phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
|
||||
|
||||
phy-type = <0>; // 0: DPHY, 1: CPHY
|
||||
auto-deskew = <0x80>;
|
||||
data-lane-num = <4>;
|
||||
data-lane-map = <0xe>;
|
||||
vc-ext-en = <0>;
|
||||
};
|
||||
};
|
||||
/* MIPI TXPHY config end */
|
||||
|
||||
/* local device extra init sequence */
|
||||
extra-init-sequence {
|
||||
status = "disabled";
|
||||
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
// common init sequence such as fsync / gpio and so on
|
||||
];
|
||||
};
|
||||
};
|
||||
/* serdes local device end */
|
||||
|
||||
/* i2c-mux start */
|
||||
i2c-mux {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser0: max96717@51 {
|
||||
compatible = "maxim,ser,max96717";
|
||||
reg = <0x51>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam0: sc320at@31 {
|
||||
compatible = "maxim,smartsens,sc320at";
|
||||
reg = <0x31>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser0>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam0_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser1: max96717@52 {
|
||||
compatible = "maxim,ser,max96717";
|
||||
reg = <0x52>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam1: sc320at@32 {
|
||||
compatible = "maxim,smartsens,sc320at";
|
||||
reg = <0x32>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser1>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <1>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam1_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser2: max96717@53 {
|
||||
compatible = "maxim,ser,max96717";
|
||||
reg = <0x53>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam2: sc320at@33 {
|
||||
compatible = "maxim,smartsens,sc320at";
|
||||
reg = <0x33>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser2>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <2>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam2_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
// Note: Serializer node defined before camera node
|
||||
max96712_dphy0_ser3: max96717@54 {
|
||||
compatible = "maxim,ser,max96717";
|
||||
reg = <0x54>;
|
||||
|
||||
ser-i2c-addr-def = <0x40>;
|
||||
|
||||
ser-init-sequence {
|
||||
seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
|
||||
reg-addr-len = <2>; // 1: 8bits, 2: 16bits
|
||||
reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
|
||||
|
||||
// reg_addr reg_val val_mask delay
|
||||
init-sequence = [
|
||||
03 02 10 00 00
|
||||
14 17 00 00 00
|
||||
14 32 7f 00 00
|
||||
];
|
||||
};
|
||||
};
|
||||
|
||||
max96712_dphy0_cam3: sc320at@34 {
|
||||
compatible = "maxim,smartsens,sc320at";
|
||||
reg = <0x34>;
|
||||
|
||||
cam-i2c-addr-def = <0x30>;
|
||||
|
||||
cam-remote-ser = <&max96712_dphy0_ser3>; // remote serializer
|
||||
|
||||
poc-supply = <&max96712_dphy0_poc_regulator>;
|
||||
|
||||
rockchip,camera-module-index = <3>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "default";
|
||||
rockchip,camera-module-lens-name = "default";
|
||||
|
||||
/* port config start */
|
||||
port {
|
||||
max96712_dphy0_cam3_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
/* port config end */
|
||||
};
|
||||
};
|
||||
};
|
||||
/* i2c-mux end */
|
||||
};
|
||||
};
|
||||
|
||||
&mipi1_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi1_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi1_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds1 {
|
||||
status = "okay";
|
||||
/* parameters for do cif reset detecting:
|
||||
* index0: monitor mode,
|
||||
0 for idle,
|
||||
1 for continue,
|
||||
2 for trigger,
|
||||
3 for hotplug (for nextchip)
|
||||
* index1: the frame id to start timer,
|
||||
min is 2
|
||||
* index2: frame num of monitoring cycle
|
||||
* index3: err time for keep monitoring
|
||||
after finding out err (ms)
|
||||
* index4: csi2 err reference val for resetting
|
||||
*/
|
||||
rockchip,cif-monitor = <3 2 1 1000 5>;
|
||||
|
||||
port {
|
||||
cif_mipi1_in: endpoint {
|
||||
remote-endpoint = <&mipi1_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
rockchip,android-usb-camerahal-enable;
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
max96712-dphy0 {
|
||||
max96712_dphy0_pwdn: max96712-dphy0-pwdn {
|
||||
rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
|
||||
};
|
||||
|
||||
max96712_dphy0_errb: max96712-dphy0-errb {
|
||||
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
|
||||
max96712_dphy0_lock: max96712-dphy0-lock {
|
||||
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
nca9539_vdd: nca9539-vdd3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "nca9539_vdd";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <20>; // NCA9539 POR
|
||||
vin-supply = <&vcc_3v3_s0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0m1_xfer>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
i2c0_nca9539_gpio: gpio@75 {
|
||||
status = "okay";
|
||||
compatible = "novo,nca9539-gpio";
|
||||
reg = <0x75>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
vdd-supply = <&nca9539_vdd>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
pinctrl-0 = <&i2c7m1_xfer>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
i2c7_nca9539_gpio: gpio@74 {
|
||||
status = "okay";
|
||||
compatible = "novo,nca9539-gpio";
|
||||
reg = <0x74>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
vdd-supply = <&nca9539_vdd>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
522
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dts
Normal file
522
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dts
Normal file
@@ -0,0 +1,522 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3576.dtsi"
|
||||
#include "rk3576-vehicle-evb-v20.dtsi"
|
||||
#include "rk3576-vehicle-evb-v20-nca9539-io-expander.dtsi"
|
||||
#include "rk3576-vehicle-evb-v20-serdes-mfd-display-maxim.dtsi"
|
||||
#include "rk3576-vehicle-evb-v20-maxim-max96712-dphy0-isx021.dtsi"
|
||||
#include "rk3576-android.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3576 VEHICLE EVB V20 Board";
|
||||
compatible = "rockchip,rk3576-vehicle-evb-v20", "rockchip,rk3576";
|
||||
|
||||
vehicle_dummy: vehicle-dummy {
|
||||
status = "okay";
|
||||
compatible = "rockchip,vehicle-dummy-adc";
|
||||
io-channels = <&saradc 4>, <&saradc 5>, <&saradc 6>;
|
||||
io-channel-names = "gear", "turn_left", "turn_right";
|
||||
};
|
||||
|
||||
vcc5v0_buck: vcc5v0-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_buck_en>;
|
||||
startup-delay-us = <2500>;
|
||||
off-on-delay-us = <1500>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster_power_buck: cluster_power-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cluster_power_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
//enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <&vcc_1v8_s0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cluster_buck_en>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_otg0_vcc5v_buck: usb_otg0_vcc5v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg0_vcc5v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host_vcc5v_buck: usb_host_vcc5v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_host_vcc5v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd1_vcc12v_buck: lcd1_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd1_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd2_vcc12v_buck: lcd2_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd2_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd1_ser_vcc5v_buck: lcd1_ser_vcc5v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd1_ser_vcc5v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd2_ser_vcc5v_buck: lcd2_ser_vcc5v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd2_ser_vcc5v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
adsp_vcc12v_buck: adsp_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "adsp_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c0_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd3_vcc12v_buck: lcd3_vcc12v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd3_vcc12v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd3_vcc5v_buck: lcd3_vcc5v-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd3_vcc5v_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck1: dcphy0_vcc12v-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 3 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck2: dcphy0_vcc12v-buck2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck3: dcphy0_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dcphy0_vcc12v_buck4: dcphy0_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dcphy0_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck1: dphy0_vcc12v-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck2: dphy0_vcc12v-buck2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck3: dphy0_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 9 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy0_vcc12v_buck4: dphy0_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy0_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck1: dphy3_vcc12v-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck1";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 11 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck2: dphy3_vcc12v-buck2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck2";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 12 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck3: dphy3_vcc12v-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck3";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 13 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
dphy3_vcc12v_buck4: dphy3_vcc12v-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dphy3_vcc12v_buck4";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
gpio = <&i2c7_nca9539_gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <12000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&hym8563 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*edp*/
|
||||
&i2c3_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd1_vcc12v_buck>;
|
||||
};
|
||||
|
||||
/*edp touch*/
|
||||
&i2c3_himax {
|
||||
himax,irq-gpio = <&gpio3 RK_PD6 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
/*dp*/
|
||||
&i2c5_max96745 {
|
||||
lock-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c5_ilitek {
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/*dp*/
|
||||
&i2c5_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd2_vcc12v_buck>;
|
||||
};
|
||||
|
||||
/*dsi*/
|
||||
&i2c8_max96752 {
|
||||
use-reg-check-work;
|
||||
vpower-supply = <&lcd3_vcc12v_buck>;
|
||||
};
|
||||
|
||||
&dp2lvds_backlight0 {
|
||||
pwms = <&pwm2_8ch_7 0 25000 0>;
|
||||
};
|
||||
|
||||
&edp2lvds_backlight0 {
|
||||
pwms = <&pwm0_2ch_0 0 25000 0>;
|
||||
};
|
||||
|
||||
/* edp->serdes->lvds_panel */
|
||||
&pwm0_2ch_0 {
|
||||
pinctrl-0 = <&pwm0m3_ch0>;
|
||||
};
|
||||
|
||||
/* dp->serdes->lvds_panel */
|
||||
&pwm2_8ch_7 {
|
||||
pinctrl-0 = <&pwm2m3_ch7>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
touch {
|
||||
//dsi-i2c8
|
||||
touch_gpio_dsi: touch-gpio-dsi {
|
||||
rockchip,pins =
|
||||
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
//dp-i2c5
|
||||
touch_gpio_dp: touch-gpio-dp {
|
||||
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
//edp0-i2c3
|
||||
touch_gpio_edp: touch-gpio-edp {
|
||||
rockchip,pins =
|
||||
<3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0-buck {
|
||||
vcc5v0_buck_en: vcc5v0-buck-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster-buck {
|
||||
cluster_buck_en: cluster-buck-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkvpss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvpss_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvpss_vir0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
468
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dtsi
Normal file
468
arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dtsi
Normal file
@@ -0,0 +1,468 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3576-vehicle.dtsi"
|
||||
#include "rk3576-rk806.dtsi"
|
||||
|
||||
/ {
|
||||
vcc5v0_buck: vcc5v0-buck {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_buck";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_buck_en>;
|
||||
startup-delay-us = <2500>;
|
||||
off-on-delay-us = <1500>;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: vcc-1v8-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8_s3>;
|
||||
};
|
||||
|
||||
vcc_3v3_s0: vcc-3v3-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
vcc_ufs_s0: vcc-ufs-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_ufs_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc1v8_ufs_vccq2_s0: vcc1v8-ufs-vccq2-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_ufs_vccq2_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8_s3>;
|
||||
};
|
||||
|
||||
vcc1v2_ufs_vccq_s0: vcc1v2-ufs-vccq-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v2_ufs_vccq_s0";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_lcd_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd0_n";
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc_3v3_s0>;
|
||||
};
|
||||
|
||||
vcc5v0_host_usb30: vcc5v0-host-usb30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host_usb30";
|
||||
//regulator-boot-on;
|
||||
//regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_host3_pwren>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_usb20: vcc5v0-otg-usb20 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg_usb20";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
//enable-active-high;
|
||||
gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg0_pwren>;
|
||||
startup-delay-us = <2000>;
|
||||
off-on-delay-us = <16000>;
|
||||
vin-supply = <&vcc5v0_buck>;
|
||||
};
|
||||
|
||||
dummy_codec: dummy-codec {
|
||||
status = "okay";
|
||||
compatible = "rockchip,dummy-codec";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
vehicle_adsp_sound: vehicle-adsp-sound {
|
||||
status = "okay";
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "rockchip,car-rk3308-sound";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai1>;
|
||||
dai-tdm-slot-num = <8>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&dummy_codec>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_psu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp0_in_vp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* mipidcphy0 needs to be enabled
|
||||
* when dsi is enabled
|
||||
*/
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð0m0_miim
|
||||
ð0m0_tx_bus2
|
||||
ð0m0_rx_bus2
|
||||
ð0m0_rgmii_clk
|
||||
ð0m0_rgmii_bus
|
||||
&phydisb>;
|
||||
|
||||
tx_delay = <0x20>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð1m0_miim
|
||||
ð1m0_tx_bus2
|
||||
ð1m0_rx_bus2
|
||||
ð1m0_rgmii_clk
|
||||
ð1m0_rgmii_bus
|
||||
ðm0_clk1_25m_out>;
|
||||
|
||||
tx_delay = <0x20>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
>1x {
|
||||
status = "disabled";
|
||||
power-supply = <&vcc3v3_lcd_n>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "disabled";
|
||||
enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&hdmi_in_vp0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&s35390a_int>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
es8388: es8388@10 {
|
||||
status = "okay";
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "everest,es8388", "everest,es8323";
|
||||
reg = <0x10>;
|
||||
clocks = <&mclkout_sai1>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&mclkout_sai1>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai1m0_mclk>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m1_xfer>;
|
||||
|
||||
icm42607_acc: icm_acc@68 {
|
||||
status = "okay";
|
||||
compatible = "icm42607_acc";
|
||||
reg = <0x68>;
|
||||
irq-gpio = <&gpio1 RK_PD5 IRQ_TYPE_EDGE_RISING>;
|
||||
irq_enable = <0>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_ACCEL>;
|
||||
layout = <4>;
|
||||
};
|
||||
|
||||
icm42607_gyro: icm_gyro@68 {
|
||||
status = "okay";
|
||||
compatible = "icm42607_gyro";
|
||||
reg = <0x68>;
|
||||
poll_delay_ms = <30>;
|
||||
type = <SENSOR_TYPE_GYROSCOPE>;
|
||||
layout = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru REFCLKO25M_GMAC0_OUT>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru REFCLKO25M_GMAC1_OUT>;
|
||||
};
|
||||
};
|
||||
|
||||
&mipidcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
reset-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,skip-scan-in-resume;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_poweren_gpio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pdm1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default", "idle", "clk";
|
||||
pinctrl-0 = <&pdm1m1_sdi0
|
||||
&pdm1m1_sdi1
|
||||
&pdm1m1_sdi2
|
||||
&pdm1m1_sdi3>;
|
||||
pinctrl-1 = <&pdm1m1_clk0_idle
|
||||
&pdm1m1_clk1_idle>;
|
||||
pinctrl-2 = <&pdm1m1_clk0
|
||||
&pdm1m1_clk1>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gmac0 {
|
||||
phydisb: phydisb {
|
||||
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
s35390a {
|
||||
s35390a_int: s35390a-int {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
usb_host3_pwren: usb-host3-pwren {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
usb_otg0_pwren: usb-otg0-pwren {
|
||||
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0-buck {
|
||||
vcc5v0_buck_en: vcc5v0-buck-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart4_gpios: uart4-gpios {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
wifi_poweren_gpio: wifi-poweren-gpio {
|
||||
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&route_hdmi {
|
||||
status = "disabled";
|
||||
connect = <&vp0_out_hdmi>;
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai1m0_lrck
|
||||
&sai1m0_sclk
|
||||
&sai1m0_sdi0
|
||||
&sai1m0_sdi1
|
||||
&sai1m0_sdo0
|
||||
&sai1m0_sdo1
|
||||
&sai1m0_sdo2>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
max-freq = <50000000>; /* spi internal clk, don't modify */
|
||||
pinctrl-names = "default", "high_speed";
|
||||
pinctrl-0 = <&spi1m1_csn0 &spi1m1_pins>;
|
||||
spi_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
};
|
||||
|
||||
&ufs {
|
||||
vcc-supply = <&vcc_ufs_s0>;
|
||||
vccq-supply = <&vcc1v2_ufs_vccq_s0>;
|
||||
vccq2-supply = <&vcc1v8_ufs_vccq2_s0>;
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
rockchip,sel-pipe-phystatus;
|
||||
rockchip,dis-u2-susphy;
|
||||
//vbus-supply = <&vcc5v0_otg_usb20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host_usb30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy {
|
||||
rockchip,dp-lane-mux = < 0 1 2 3 >;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy_dp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy_u3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_drd0_dwc3 {
|
||||
phys = <&u2phy0_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "peripheral";
|
||||
maximum-speed = "high-speed";
|
||||
extcon = <&u2phy0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_drd1_dwc3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -540,7 +540,7 @@
|
||||
};
|
||||
|
||||
|
||||
himax@45 {
|
||||
i2c8_himax: i2c8-himax@45 {
|
||||
compatible = "himax,hxcommon";
|
||||
reg = <0x45>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
@@ -1067,7 +1067,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ilitek@41 {
|
||||
i2c5_ilitek: i2c5-ilitek@41 {
|
||||
compatible = "ilitek,ili251x";
|
||||
reg = <0x41>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
@@ -1595,7 +1595,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
himax@45 {
|
||||
i2c2_himax: i2c2-himax@45 {
|
||||
compatible = "himax,hxcommon";
|
||||
reg = <0x45>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
@@ -1592,13 +1592,12 @@ static inline int _setup_xfer_cyclic(struct pl330_dmac *pl330,
|
||||
*/
|
||||
static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
|
||||
struct pl330_thread *thrd, unsigned index,
|
||||
struct _xfer_spec *pxs)
|
||||
struct _xfer_spec *pxs, int off)
|
||||
{
|
||||
struct _pl330_req *req = &thrd->req[index];
|
||||
u8 *buf = req->mc_cpu;
|
||||
int off = 0;
|
||||
|
||||
PL330_DBGMC_START(req->mc_bus);
|
||||
PL330_DBGMC_START(req->mc_bus + off);
|
||||
|
||||
/* DMAMOV CCR, ccr */
|
||||
off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
|
||||
@@ -1606,10 +1605,13 @@ static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
|
||||
if (!pxs->desc->cyclic) {
|
||||
off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
|
||||
|
||||
/* DMASEV peripheral/event */
|
||||
off += _emit_SEV(dry_run, &buf[off], thrd->ev);
|
||||
/* DMAEND */
|
||||
off += _emit_END(dry_run, &buf[off]);
|
||||
if (pxs->desc->last) {
|
||||
/* DMASEV peripheral/event */
|
||||
off += _emit_SEV(dry_run, &buf[off], thrd->ev);
|
||||
|
||||
/* DMAEND */
|
||||
off += _emit_END(dry_run, &buf[off]);
|
||||
}
|
||||
} else {
|
||||
off += _setup_xfer_cyclic(pl330, dry_run, &buf[off],
|
||||
pxs, thrd->ev);
|
||||
@@ -1656,7 +1658,7 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
|
||||
* xfer units are done or some error occurs.
|
||||
*/
|
||||
static int pl330_submit_req(struct pl330_thread *thrd,
|
||||
struct dma_pl330_desc *desc)
|
||||
struct dma_pl330_desc *desc, int *off)
|
||||
{
|
||||
struct pl330_dmac *pl330 = thrd->dmac;
|
||||
struct _xfer_spec xs;
|
||||
@@ -1712,12 +1714,14 @@ static int pl330_submit_req(struct pl330_thread *thrd,
|
||||
|
||||
idx = thrd->req[0].desc == NULL ? 0 : 1;
|
||||
|
||||
dev_dbg(pl330->ddma.dev, "desc-%px id %d-%d off %03d last %d cyclic %d\n",
|
||||
desc, thrd->id, idx, *off, desc->last, desc->cyclic);
|
||||
|
||||
xs.ccr = ccr;
|
||||
xs.desc = desc;
|
||||
|
||||
/* First dry run to check if req is acceptable */
|
||||
ret = _setup_req(pl330, 1, thrd, idx, &xs);
|
||||
|
||||
ret = _setup_req(pl330, 1, thrd, idx, &xs, *off);
|
||||
if (ret > pl330->mcbufsz / 2) {
|
||||
dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
|
||||
__func__, __LINE__, ret, pl330->mcbufsz / 2);
|
||||
@@ -1726,13 +1730,26 @@ static int pl330_submit_req(struct pl330_thread *thrd,
|
||||
}
|
||||
|
||||
/* Hook the request */
|
||||
thrd->lstenq = idx;
|
||||
thrd->req[idx].desc = desc;
|
||||
_setup_req(pl330, 0, thrd, idx, &xs);
|
||||
if (desc->last) {
|
||||
thrd->lstenq = idx;
|
||||
thrd->req[idx].desc = desc;
|
||||
}
|
||||
|
||||
*off = _setup_req(pl330, 0, thrd, idx, &xs, *off);
|
||||
|
||||
if (!desc->last) {
|
||||
desc->status = FREE;
|
||||
list_move_tail(&desc->node, &pl330->desc_pool);
|
||||
|
||||
dev_dbg(pl330->ddma.dev, "desc-%px has been merged, drop it\n", desc);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
xfer_exit:
|
||||
if (desc->last)
|
||||
*off = 0;
|
||||
|
||||
spin_unlock_irqrestore(&pl330->lock, flags);
|
||||
|
||||
return ret;
|
||||
@@ -2227,16 +2244,16 @@ to_desc(struct dma_async_tx_descriptor *tx)
|
||||
|
||||
static inline void fill_queue(struct dma_pl330_chan *pch)
|
||||
{
|
||||
struct dma_pl330_desc *desc;
|
||||
int ret;
|
||||
struct dma_pl330_desc *desc, *_dt;
|
||||
int ret, off = 0;
|
||||
|
||||
list_for_each_entry(desc, &pch->work_list, node) {
|
||||
list_for_each_entry_safe(desc, _dt, &pch->work_list, node) {
|
||||
|
||||
/* If already submitted */
|
||||
if (desc->status == BUSY || desc->status == PAUSED)
|
||||
continue;
|
||||
|
||||
ret = pl330_submit_req(pch->thread, desc);
|
||||
ret = pl330_submit_req(pch->thread, desc, &off);
|
||||
if (!ret) {
|
||||
desc->status = BUSY;
|
||||
} else if (ret == -EAGAIN) {
|
||||
@@ -2999,19 +3016,17 @@ static struct dma_async_tx_descriptor *pl330_prep_interleaved_dma(
|
||||
}
|
||||
|
||||
if (xt->dir == DMA_MEM_TO_DEV) {
|
||||
desc->rqcfg.src_inc = 1;
|
||||
desc->rqcfg.dst_inc = 0;
|
||||
src = xt->src_start;
|
||||
dst = pch->fifo_dma;
|
||||
full_buffer_bytes = (size + src_icg) * numf;
|
||||
} else {
|
||||
desc->rqcfg.src_inc = 0;
|
||||
desc->rqcfg.dst_inc = 1;
|
||||
src = pch->fifo_dma;
|
||||
dst = xt->dst_start;
|
||||
full_buffer_bytes = (size + dst_icg) * numf;
|
||||
}
|
||||
|
||||
desc->rqcfg.src_inc = xt->src_inc;
|
||||
desc->rqcfg.dst_inc = xt->dst_inc;
|
||||
desc->rqtype = xt->dir;
|
||||
desc->rqcfg.brst_size = pch->burst_sz;
|
||||
desc->rqcfg.brst_len = pch->burst_len;
|
||||
|
||||
@@ -1416,12 +1416,7 @@ static irqreturn_t rk3576_hdmi_thread(int irq, void *dev_id)
|
||||
|
||||
if (stat) {
|
||||
hdmi->hpd_stat = true;
|
||||
/*
|
||||
* Responding to hpd too early will cause the hdmi frl
|
||||
* hfr1-10 test to fail. The ln3 value of TE should have
|
||||
* been 3 but changed to 0.
|
||||
*/
|
||||
msecs = 450;
|
||||
msecs = 150;
|
||||
} else {
|
||||
hdmi->hpd_stat = false;
|
||||
msecs = 20;
|
||||
|
||||
@@ -140,6 +140,7 @@ static int gsensor_report_value(struct i2c_client *client,
|
||||
input_report_abs(sensor->input_dev, ABS_X, axis->x);
|
||||
input_report_abs(sensor->input_dev, ABS_Y, axis->y);
|
||||
input_report_abs(sensor->input_dev, ABS_Z, axis->z);
|
||||
input_sync(sensor->input_dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -328,6 +328,7 @@ static void rk628_bt1120_hdmirx_reset(struct v4l2_subdev *sd)
|
||||
{
|
||||
struct rk628_bt1120 *bt1120 = to_bt1120(sd);
|
||||
|
||||
rk628_hdmirx_audio_cancel_work_audio(bt1120->audio_info, true);
|
||||
disable_irq(bt1120->plugin_irq);
|
||||
disable_irq(bt1120->hdmirx_irq);
|
||||
rk628_hdmirx_controller_reset(bt1120->rk628);
|
||||
|
||||
@@ -473,6 +473,7 @@ static void rk628_csi_hdmirx_reset(struct v4l2_subdev *sd)
|
||||
{
|
||||
struct rk628_csi *csi = to_csi(sd);
|
||||
|
||||
rk628_hdmirx_audio_cancel_work_audio(csi->audio_info, true);
|
||||
disable_irq(csi->plugin_irq);
|
||||
disable_irq(csi->hdmirx_irq);
|
||||
rk628_hdmirx_controller_reset(csi->rk628);
|
||||
|
||||
@@ -1218,6 +1218,42 @@ static int rk_pcie_init_irq_and_wq(struct rk_pcie *rk_pcie, struct platform_devi
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_pcie_host_config(struct rk_pcie *rk_pcie)
|
||||
{
|
||||
struct dw_pcie *pci = rk_pcie->pci;
|
||||
u32 val;
|
||||
|
||||
if (rk_pcie->is_lpbk) {
|
||||
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
|
||||
val |= PORT_LINK_LPBK_ENABLE;
|
||||
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
|
||||
}
|
||||
|
||||
if (rk_pcie->is_comp && rk_pcie->comp_prst[0]) {
|
||||
val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
|
||||
val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12);
|
||||
dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
|
||||
}
|
||||
|
||||
/* Enable RASDES Error event by default */
|
||||
val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_VNDR);
|
||||
if (!val) {
|
||||
dev_err(pci->dev, "Unable to find RASDES CAP!\n");
|
||||
} else {
|
||||
dw_pcie_writel_dbi(pci, val + 8, 0x1c);
|
||||
dw_pcie_writel_dbi(pci, val + 8, 0x3);
|
||||
rk_pcie->have_rasdes = true;
|
||||
}
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
|
||||
rk_pcie_fast_link_setup(rk_pcie);
|
||||
|
||||
rk_pcie_set_rc_mode(rk_pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_pcie_really_probe(void *p)
|
||||
{
|
||||
struct platform_device *pdev = p;
|
||||
@@ -1227,7 +1263,6 @@ static int rk_pcie_really_probe(void *p)
|
||||
int ret;
|
||||
const struct of_device_id *match;
|
||||
const struct rk_pcie_of_data *data;
|
||||
u32 val = 0;
|
||||
|
||||
/* 1. resource initialization */
|
||||
match = of_match_device(rk_pcie_of_match, dev);
|
||||
@@ -1291,27 +1326,11 @@ static int rk_pcie_really_probe(void *p)
|
||||
goto disable_clk;
|
||||
}
|
||||
|
||||
/* 5. signal test and capability settings */
|
||||
if (rk_pcie->is_lpbk) {
|
||||
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
|
||||
val |= PORT_LINK_LPBK_ENABLE;
|
||||
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
|
||||
}
|
||||
|
||||
if (rk_pcie->is_comp && rk_pcie->comp_prst[0]) {
|
||||
val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
|
||||
val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12);
|
||||
dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
|
||||
}
|
||||
|
||||
/* Enable RASDES Error event by default */
|
||||
val = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_VNDR);
|
||||
if (!val) {
|
||||
dev_err(pci->dev, "Unable to find RASDES CAP!\n");
|
||||
} else {
|
||||
dw_pcie_writel_dbi(pci, val + 8, 0x1c);
|
||||
dw_pcie_writel_dbi(pci, val + 8, 0x3);
|
||||
rk_pcie->have_rasdes = true;
|
||||
/* 5. host registers manipulation */
|
||||
ret = rk_pcie_host_config(rk_pcie);
|
||||
if (ret) {
|
||||
dev_err_probe(dev, ret, "rk_pcie_host_config failed\n");
|
||||
goto disable_clk;
|
||||
}
|
||||
|
||||
/* 6. software process */
|
||||
@@ -1319,12 +1338,6 @@ static int rk_pcie_really_probe(void *p)
|
||||
if (ret)
|
||||
goto disable_phy;
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
|
||||
rk_pcie_fast_link_setup(rk_pcie);
|
||||
|
||||
rk_pcie_set_rc_mode(rk_pcie);
|
||||
|
||||
ret = rk_add_pcie_port(rk_pcie, pdev);
|
||||
|
||||
if (rk_pcie->is_signal_test == true)
|
||||
|
||||
@@ -439,7 +439,7 @@ static int rk_dailink_init(struct snd_soc_pcm_runtime *rtd)
|
||||
mc_data->rx_slot_mask,
|
||||
mc_data->slots,
|
||||
mc_data->slot_width);
|
||||
if (ret && ret != -EOPNOTSUPP) {
|
||||
if (ret && ret != -ENOTSUPP) {
|
||||
dev_err(card->dev, "cpu_dai: set_tdm_slot error\n");
|
||||
return ret;
|
||||
}
|
||||
@@ -450,7 +450,7 @@ static int rk_dailink_init(struct snd_soc_pcm_runtime *rtd)
|
||||
mc_data->rx_slot_mask,
|
||||
mc_data->slots,
|
||||
mc_data->slot_width);
|
||||
if (ret && ret != -EOPNOTSUPP) {
|
||||
if (ret && ret != -ENOTSUPP) {
|
||||
dev_err(card->dev, "codec_dai: set_tdm_slot error\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user