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UPSTREAM: arm64: mm: Rename post_ttbr0_update_workaround

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The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1.
Since we're using TTBR1 for the ASID, rename the hook to make it clearer
as to what it's doing.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 158d495899)

[toddpoynor@google.com: fixup context conflict in comments]
Change-Id: Ia0f82eee78ad442d1773245b99c7534f0ea066e4
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Will Deacon
2017-08-10 13:34:30 +01:00
committed by Greg Kroah-Hartman
parent a72dd8a676
commit 071a49fc82
3 changed files with 4 additions and 4 deletions
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4
arch/arm64/include/asm/assembler.h
View File

@@ -430,9 +430,9 @@ alternative_endif
.endm
/*
* Errata workaround post TTBR0_EL1 update.
* Errata workaround post TTBRx_EL1 update.
*/
.macro post_ttbr0_update_workaround
.macro post_ttbr_update_workaround
#ifdef CONFIG_CAVIUM_ERRATUM_27456
alternative_if ARM64_WORKAROUND_CAVIUM_27456
ic iallu

2
arch/arm64/kernel/entry.S
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@@ -205,7 +205,7 @@ alternative_else_nop_endif
* Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
* corruption).
*/
post_ttbr0_update_workaround
post_ttbr_update_workaround
.endif
1:
.if \el != 0

2
arch/arm64/mm/proc.S
View File

@@ -139,7 +139,7 @@ ENTRY(cpu_do_switch_mm)
isb
msr ttbr0_el1, x0 // now update TTBR0
isb
post_ttbr0_update_workaround
post_ttbr_update_workaround
ret
ENDPROC(cpu_do_switch_mm)