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vpp: sr: disable core0 and core1 scaler latch [1/1]

Browse Source 
PD#SWPL-3144

Problem:
The latch function cause the super scaler size asynchronous

Solution:
Disable sr core0 and core1 scaler latch

Verify:
T962x2 x301 board test pass

Change-Id: Iecbcc3e0c751093b6515f7b46973eca2157cd349
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-12-26 18:55:36 +08:00
committed by Luan Yuan
parent 2202bcd709
commit 073697cfea
2 changed files with 14 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/amlogic/media/video_sink/video.c
View File

@@ -10322,10 +10322,19 @@ static int __init video_early_init(void)
DMC_AM0_CHAN_CTRL,
0x8ff403cf);
/* force bypass dolby for TL1. There is no dolby function */
if (is_meson_tl1_cpu())
if (is_meson_tl1_cpu()) {
/* force bypass dolby for TL1, no dolby function */
WRITE_VCBUS_REG_BITS(
DOLBY_PATH_CTRL, 0xf, 0, 6);
/* disable latch for sr core0/1 scaler */
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
WRITE_VCBUS_REG_BITS(
SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1);
}
if (is_meson_g12b_cpu())
WRITE_VCBUS_REG_BITS(
SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
return 0;
}

3
include/linux/amlogic/media/registers/regs/vpp_regs.h
View File

@@ -245,5 +245,8 @@
#define OSD1_BLEND_SRC_CTRL 0x1dfd
#define OSD2_BLEND_SRC_CTRL 0x1dfe
/* after g12b */
#define SRSHARP0_SHARP_SYNC_CTRL 0x3eb0
#define SRSHARP1_SHARP_SYNC_CTRL 0x3fb0
#endif