PCI: rockchip: dw: Increase N_FTS needed by L0s exit

FTS, fast training sequences, is used for exiting from L0s, which
is issued to peers while in TS1 phase. If number of FTS issued is
not enough for PHY itself, FTS timeout would occur and the LTSMM
will fall into recovery leading to longer exit latency.

In theory this value is PHY relevant, especially combophy needs a
bigger FTS that another one. The default value is 210, just increase
it to 255 the max for compatibility.

Another thing should be noted is if EP can't work stable under L0s
or failing to do FTS in requested, just add them to quirk.c and there
were numbers of buggy devices already there who claims to support L0s but
actually not.

Change-Id: I071c27ef6a3ac504b9ed82b748b41ec55bfd5fc5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

drivers/pci/controller/dwc/pcie-dw-rockchip.c

@@ -1566,6 +1566,8 @@ static int rk_pcie_host_config(struct rk_pcie *rk_pcie)
 
 	/* Enable L0s capability */
 	if (rk_pcie->linkcap_off) {
+		pci->n_fts[0] = 255; /* Gen1 */
+		pci->n_fts[1] = 255; /* Gen2+ */
 		val = dw_pcie_readl_dbi(rk_pcie->pci, rk_pcie->linkcap_off);
 		val |= PCI_EXP_LNKCAP_ASPM_L0S;
 		dw_pcie_writel_dbi(rk_pcie->pci, rk_pcie->linkcap_off, val);