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rk312x: set suspend voltage(arm and logic) 1050mV

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Signed-off-by: 许盛飞 <xsf@rock-chips.com>
This commit is contained in:
许盛飞
2014-09-11 11:26:10 +08:00
parent e0a50c334f
commit 0777fe09d6
3 changed files with 27 additions and 71 deletions
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94
arch/arm/mach-rockchip/pm-rk312x.c
View File

@@ -152,7 +152,7 @@ static inline void plls_resume(u32 pll_id)
{
u32 pllcon0, pllcon1, pllcon2;
cru_writel(RK312X_PLL_MODE_SLOW(pll_id), RK312X_CRU_MODE_CON);
/*cru_writel(RK312X_PLL_MODE_SLOW(pll_id), RK312X_CRU_MODE_CON);*/
/*cru_writel(RK312X_PLL_NOBYPASS, RK312x_PLL_CONS((pll_id), 0));*/
pllcon0 = plls_con0_save[pll_id];
@@ -220,25 +220,20 @@ static void pm_plls_suspend(void)
static void pm_plls_resume(void)
{
plls_resume(APLL_ID);
cru_writel(clk_sel0 | CRU_W_MSK(0, 0x1f), RK312X_CRU_CLKSELS_CON(0));
cru_writel(clk_sel1 | CRU_W_MSK(0, 0x7), RK312X_CRU_CLKSELS_CON(1));
plls_resume(APLL_ID);
cru_writel(cru_mode_con
|(RK312X_PLL_MODE_MSK(APLL_ID) << 16), RK312X_CRU_MODE_CON);
/* pmu alive */
plls_resume(GPLL_ID);
/*peri aclk hclk pclk*/
cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
| CRU_W_MSK(12, 0x3)), RK312X_CRU_CLKSELS_CON(10));
/* crypto*/
cru_writel(clk_sel24 | CRU_W_MSK(0, 0x3), RK312X_CRU_CLKSELS_CON(24));
cru_writel(clk_sel29 | CRU_W_MSK(8, 0x1f), RK312X_CRU_CLKSELS_CON(29));
/* pmu alive */
plls_resume(GPLL_ID);
cru_writel(cru_mode_con | (RK312X_PLL_MODE_MSK(GPLL_ID) << 16)
, RK312X_CRU_MODE_CON);
@@ -903,86 +898,42 @@ static void pmic_sleep_gpio_get_dts_info(struct device_node *parent)
void PIE_FUNC(ddr_suspend)(void);
void PIE_FUNC(ddr_resume)(void);
static __sramdata u32 rkpm_pwm_duty0;
static __sramdata u32 rkpm_pwm_duty1;
static __sramdata u32 rkpm_pwm_duty2;
#define PWM_VOLTAGE 0x600
void PIE_FUNC(pwm_regulator_suspend)(void)
{
int gpio0_inout;
int gpio0_ddr;
int clk_gates8;
clk_gates8 = cru_readl(0xf0);
cru_writel(0x1e000000, 0xf0);
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
grf_writel(0x00100000, 0xb4);/*iomux gpio0d2*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x04000000
, RK_GPIO_VIRT(0) + 0x04);
dsb();
writel_relaxed(gpio0_ddr | 0x04000000, RK_GPIO_VIRT(0));
rkpm_pwm_duty0 = readl_relaxed(RK_PWM_VIRT + 0x08);
writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x08);
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
grf_writel(0x00400000, 0xb4);/*iomux gpio0d3*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x08000000
, RK_GPIO_VIRT(0) + 0x04);
dsb();
writel_relaxed(gpio0_ddr | 0x08000000, RK_GPIO_VIRT(0));
rkpm_pwm_duty1 = readl_relaxed(RK_PWM_VIRT + 0x18);
writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x18);
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
grf_writel(0x01000000, 0xb4);/*iomux gpio0d2*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x10000000, RK_GPIO_VIRT(0) + 0x04);
dsb();
writel_relaxed(gpio0_ddr | 0x10000000, RK_GPIO_VIRT(0));
rkpm_pwm_duty2 = readl_relaxed(RK_PWM_VIRT + 0x28);
writel_relaxed(PWM_VOLTAGE, RK_PWM_VIRT + 0x28);
}
cru_writel(0x1e000000 | clk_gates8, 0xf0);
sram_udelay(30);
}
void PIE_FUNC(pwm_regulator_resume)(void)
{
int gpio0_inout;
int gpio0_ddr;
int clk_gates8;
clk_gates8 = cru_readl(0xf0);
cru_writel(0x1e000000, 0xf0);
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0)) {
grf_writel(0x00100010, 0xb4);/*iomux gpio0d2*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x04000000, RK_GPIO_VIRT(0)
+ 0x04);
dsb();
writel_relaxed(gpio0_ddr & ~0x04000000, RK_GPIO_VIRT(0));
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM0))
writel_relaxed(rkpm_pwm_duty0, RK_PWM_VIRT + 0x08);
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1)) {
grf_writel(0x00400040, 0xb4);/*iomux gpio0d3*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x08000000, RK_GPIO_VIRT(0)
+ 0x04);
dsb();
writel_relaxed(gpio0_ddr | ~0x08000000, RK_GPIO_VIRT(0));
}
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM1))
writel_relaxed(rkpm_pwm_duty1, RK_PWM_VIRT + 0x18);
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2)) {
grf_writel(0x01001000, 0xb4);/*iomux gpio0d2*/
gpio0_inout = readl_relaxed(RK_GPIO_VIRT(0) + 0x04);
gpio0_ddr = readl_relaxed(RK_GPIO_VIRT(0));
writel_relaxed(gpio0_inout | 0x10000000, RK_GPIO_VIRT(0)
+ 0x04);
dsb();
writel_relaxed(gpio0_ddr | ~0x10000000, RK_GPIO_VIRT(0));
}
cru_writel(0x1e000000 | clk_gates8, 0xf0);
sram_udelay(30);
if (rkpm_chk_sram_ctrbit(RKPM_CTR_VOL_PWM2))
writel_relaxed(rkpm_pwm_duty2, RK_PWM_VIRT + 0x28);
}
static void reg_pread(void)
{
int i;
@@ -1012,6 +963,7 @@ static void reg_pread(void)
n = readl_relaxed(RK_GRF_VIRT);
n = readl_relaxed(RK_CRU_VIRT);
n = readl_relaxed(RK_PMU_VIRT);
n = readl_relaxed(RK_PWM_VIRT);
}
static void __init rk312x_suspend_init(void)

1
arch/arm/mach-rockchip/rk312x.c
View File

@@ -79,6 +79,7 @@ static struct map_desc rk312x_io_desc[] __initdata = {
RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
};
static void __init rk312x_boot_mode_init(void)

3
include/linux/rockchip/iomap.h
View File

@@ -17,6 +17,7 @@
#define RK_DEBUG_UART_VIRT RK_IO_ADDRESS(0x00060000)
#define RK_CPU_AXI_BUS_VIRT RK_IO_ADDRESS(0x00070000)
#define RK_TIMER_VIRT RK_IO_ADDRESS(0x00080000)
#define RK_PWM_VIRT RK_IO_ADDRESS(0x00088000)
#define RK_GIC_VIRT RK_IO_ADDRESS(0x00090000)
#define RK_BOOTRAM_VIRT RK_IO_ADDRESS(0x000a0000)
#define RK_DDR_VIRT RK_IO_ADDRESS(0x000d0000)
@@ -177,5 +178,7 @@
#define RK312X_EFUSE_SIZE RK3036_EFUSE_SIZE
#define RK312X_PMU_PHYS 0x100a0000
#define RK312X_PMU_SIZE SZ_64K
#define RK312X_PWM_PHYS 0x20050000
#define RK312X_PWM_SIZE SZ_16K
#endif