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ARM: tegra: clock: Add function to set SDMMC tap delay

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The SDMMC controllers have extra bits in the clock source
register that adjust the delay between the clock and data
to compenstate for delays on the PCB.  The values need to
be set from the clock code so the clock can be locked
during the read-modify-write on the clock source register.

Change-Id: Id25b7cc01fa4ec48478b60aefdf5e59bb040fbf2
Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross
2010-12-28 14:54:10 -08:00
parent 658a127f90
commit 0792e02b8e
4 changed files with 31 additions and 0 deletions
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11
arch/arm/mach-tegra/clock.c
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@@ -555,6 +555,17 @@ int __init tegra_late_init_clock(void)
}
late_initcall(tegra_late_init_clock);
/* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB. */
void tegra_sdmmc_tap_delay(struct clk *c, int delay) {
unsigned long flags;
clk_lock_save(c, flags);
tegra2_sdmmc_tap_delay(c, delay);
clk_unlock_restore(c, flags);
}
#ifdef CONFIG_DEBUG_FS
/*

1
arch/arm/mach-tegra/clock.h
View File

@@ -162,5 +162,6 @@ int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
void clk_set_cansleep(struct clk *c);
unsigned long clk_get_rate_locked(struct clk *c);
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif

1
arch/arm/mach-tegra/include/mach/clk.h
View File

@@ -27,5 +27,6 @@ void tegra_periph_reset_assert(struct clk *c);
int tegra_dvfs_set_rate(struct clk *c, unsigned long rate);
unsigned long clk_get_rate_all_locked(struct clk *c);
void tegra_sdmmc_tap_delay(struct clk *c, int delay);
#endif

18
arch/arm/mach-tegra/tegra2_clocks.c
View File

@@ -75,6 +75,10 @@
#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
#define SDMMC_CLK_INT_FB_SEL (1 << 23)
#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
#define PLL_BASE 0x0
#define PLL_BASE_BYPASS (1<<31)
#define PLL_BASE_ENABLE (1<<30)
@@ -1022,6 +1026,20 @@ static struct clk_ops tegra_periph_clk_ops = {
.reset = &tegra2_periph_clk_reset,
};
/* The SDMMC controllers have extra bits in the clock source register that
* adjust the delay between the clock and data to compenstate for delays
* on the PCB. */
void tegra2_sdmmc_tap_delay(struct clk *c, int delay) {
u32 reg;
delay = clamp(delay, 0, 15);
reg = clk_readl(c->reg);
reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
reg |= SDMMC_CLK_INT_FB_SEL;
reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
clk_writel(reg, c->reg);
}
/* External memory controller clock ops */
static void tegra2_emc_clk_init(struct clk *c)
{