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clk: rockchip: rv1126: Fix clk_npu gate

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Change-Id: I3e18abcc7a4e121093f16634f6926b12896f0205
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2020-03-31 17:43:34 +08:00
committed by Tao Huang
parent ed9580beef
commit 07dd39cd7f
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rv1126.c
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@@ -311,7 +311,7 @@ static struct rockchip_clk_branch rv1126_aclk_pdnpu_npu5 __initdata =
static struct rockchip_clk_branch rv1126_clk_npu_np5 __initdata =
COMPOSITE_HALFDIV(CLK_NPU_NP5, "clk_npu_np5", mux_gpll_cpll_apll_hpll_p, 0,
RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 4, 4, DFLAGS,
RV1126_CLKGATE_CON(22), 11, GFLAGS);
RV1126_CLKGATE_CON(22), 10, GFLAGS);
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
/*
@@ -1241,7 +1241,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
RV1126_CLKGATE_CON(22), 8, GFLAGS),
COMPOSITE_BROTHER(CLK_NPU_DIV, "clk_npu_div", mux_gpll_cpll_apll_hpll_p, 0,
RV1126_CLKSEL_CON(67), 8, 2, MFLAGS, 0, 4, DFLAGS,
RV1126_CLKGATE_CON(22), 10, GFLAGS,
RV1126_CLKGATE_CON(22), 9, GFLAGS,
&rv1126_clk_npu_np5),
MUX(CLK_CORE_NPU, "clk_core_npu", mux_clk_npu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
RV1126_CLKSEL_CON(67), 12, 1, MFLAGS),