hdmitx: update hdmitx mode parameters

PD#156734: hdmitx: update hdmitx mode parameters 1.update 6G signal 2.add hpd interrupt 3.add ddc channel 4.enable every mode output Change-Id: I7d505f41b4f182324e6d8c560a17fb0b2bbb6b7a Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
2026-06-07 19:30:30 +09:00 · 2018-02-22 17:08:40 +08:00
parent 14d9ad563d
commit 082e51e3f8
9 changed files with 88 additions and 54 deletions
--- a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts
@@ -112,9 +112,9 @@
 		dev_name = "amhdmitx";
 		status = "okay";
 		vend-data = <&vend_data>;
-		//pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
-		//pinctrl-0=<&hdmitx_hpd>;
-		//pinctrl-1=<&hdmitx_ddc>;
+		pinctrl-names="default", "hdmitx_i2c";
+		pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
+		pinctrl-1=<&hdmitx_hpd_gpio &c_i2c_master>;
 		clocks = <&clkc CLKID_VAPB_MUX>,
 			 <&clkc CLKID_VPU_MUX>;
 		clock-names = "hdmi_vapb_clk",
--- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts
+++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts
@@ -114,9 +114,9 @@
 		dev_name = "amhdmitx";
 		status = "okay";
 		vend-data = <&vend_data>;
-		//pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
-		//pinctrl-0=<&hdmitx_hpd>;
-		//pinctrl-1=<&hdmitx_ddc>;
+		pinctrl-names="default", "hdmitx_i2c";
+		pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>;
+		pinctrl-1=<&hdmitx_hpd_gpio &c_i2c_master>;
 		clocks = <&clkc CLKID_VAPB_MUX>,
 			 <&clkc CLKID_VPU_MUX>;
 		clock-names = "hdmi_vapb_clk",
--- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi
@@ -803,6 +803,40 @@
 		};
 	};

+	hdmitx_hpd: hdmitx_hpd {
+		mux {
+			groups = "hdmitx_hpd_in";
+			function = "hdmitx";
+			bias-disable;
+		};
+	};
+
+	hdmitx_hpd_gpio: hdmitx_hpd_gpio {
+		mux {
+			groups = "GPIOH_1";
+			function = "gpio_periphs";
+			bias-disable;
+		};
+	};
+
+	hdmitx_ddc: hdmitx_ddc {
+		mux {
+			groups = "hdmitx_sda",
+				"hdmitx_sck";
+			function = "hdmitx";
+			bias-disable;
+		};
+	};
+
+	c_i2c_master: c_i2c {
+		mux {
+			groups = "i2c0_sda_c",
+			"i2c0_sck_c";
+			function = "i2c3";
+			bias-disable;
+		};
+	};
+
 	wifi_32k_pins:wifi_32k_pins {
 		mux {
 			groups = "pwm_e";
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c
@@ -2215,32 +2215,6 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
 	return valid;
 }

-/*
- * For some TVs, their EDID declare support 2160p60hz(>3.4Gbps) on SVDs,
- * but no HF_IEEEOUT, so consider they don't support that format.
- */
-static enum hdmi_vic hdmitx_edid_recheck_format(struct hdmitx_dev *hdev,
-	enum hdmi_vic vic)
-{
-	struct rx_cap *pRXCap = &(hdev->RXCap);
-
-	switch (vic) {
-	case HDMI_3840x2160p50_16x9:
-	case HDMI_3840x2160p60_16x9:
-	case HDMI_4096x2160p50_256x135:
-	case HDMI_4096x2160p60_256x135:
-	case HDMI_3840x2160p50_64x27:
-	case HDMI_3840x2160p60_64x27:
-		break;
-	default:
-		return vic;
-	}
-
-	if (!pRXCap->HF_IEEEOUI || ((pRXCap->Max_TMDS_Clock2 * 5) < 340))
-		vic = HDMI_Unknown;
-	return vic;
-}
-
 /* force_flag: 0 means check with RX's edid */
 /* 1 means no check wich RX's edid */
 enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
@@ -2260,7 +2234,6 @@ enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
 				vic = HDMI_Unknown;
 		}
 	}
-	vic = hdmitx_edid_recheck_format(hdev, vic);
 	return vic;
 }

--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -717,7 +717,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 	  HDMI_4096x2160p25_256x135,
 	  HDMI_4096x2160p30_256x135,
 	  HDMI_VIC_END},
-		5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+		2970000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
 	{{HDMI_3840x2160p60_16x9,
 	  HDMI_3840x2160p50_16x9,
 	  HDMI_4096x2160p60_256x135,
@@ -729,7 +729,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
 	  HDMI_3840x2160p60_16x9_Y420,
 	  HDMI_3840x2160p50_16x9_Y420,
 	  HDMI_VIC_END},
-		5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+		2970000, 1, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
 	{{HDMI_VIC_FAKE,
 	  HDMI_VIC_END},
 		3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
@@ -65,11 +65,11 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 {
 	switch (clk) {
 	case 5940000:
-		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004f7);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b3a04f7);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00010000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
-		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
-		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x2a29dc00);
+		hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
 		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
@@ -116,7 +116,7 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 		WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
 		pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
 		break;
-	case 4320000:
+	case 4324320:
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
 		hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
@@ -59,7 +59,7 @@ void init_reg_map(unsigned int type);
 #define HDMITX_SEC_REG_ADDR(reg) \
 	((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + reg)
 #define HDMITX_REG_ADDR(reg) \
-	((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+	((HDMITX_REG_IDX << BASE_REG_OFFSET) + reg)
 #define ELP_ESM_REG_ADDR(reg) \
 	((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + (reg << 2))

@@ -793,11 +793,11 @@ void init_reg_map(unsigned int type);
 #define P_HDMITX_DATA_PORT_SEC HDMITX_SEC_REG_ADDR(HDMITX_DATA_PORT_SEC)
 #define HDMITX_CTRL_PORT_SEC (0x02 << 2)
 #define P_HDMITX_CTRL_PORT_SEC HDMITX_SEC_REG_ADDR(HDMITX_CTRL_PORT_SEC)
-#define HDMITX_ADDR_PORT 0x00
+#define HDMITX_ADDR_PORT (0x00 << 2)
 #define P_HDMITX_ADDR_PORT HDMITX_REG_ADDR(HDMITX_ADDR_PORT)
-#define HDMITX_DATA_PORT 0x01
+#define HDMITX_DATA_PORT (0x01 << 2)
 #define P_HDMITX_DATA_PORT HDMITX_REG_ADDR(HDMITX_DATA_PORT)
-#define HDMITX_CTRL_PORT 0x02
+#define HDMITX_CTRL_PORT (0x02 << 2)
 #define P_HDMITX_CTRL_PORT HDMITX_REG_ADDR(HDMITX_CTRL_PORT)

 #define ELP_ESM_HPI_REG_BASE 0x0
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.c
@@ -343,14 +343,28 @@ unsigned int hdmitx_rd_reg_g12a(unsigned int addr)
 	unsigned long hdmitx_addr = 0;
 	unsigned int val;

-	if (large_offset == 0x10) {
+	switch  (large_offset) {
+	case 0x10:
+		/*DWC*/
 		hdmitx_addr = HDMITX_SEC_REG_ADDR(small_offset);
 		val = readb(TO_PMAP_ADDR(hdmitx_addr));
-	} else if ((large_offset == 0x11) || (large_offset == 0x01))
+		break;
+	case 0x11:
+	case 0x01:
+		/*SECURITY DWC/TOP*/
 		val = hdmitx_rd_reg_normal(addr);
-	else {
-		hdmitx_addr = HDMITX_REG_ADDR(small_offset);
-		val = readl(TO_PMAP_ADDR(hdmitx_addr));
+		break;
+	case 00:
+	default:
+		/*TOP*/
+		if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+			hdmitx_addr = HDMITX_REG_ADDR(small_offset);
+			val = readb(TO_PMAP_ADDR(hdmitx_addr));
+		} else {
+			hdmitx_addr = HDMITX_REG_ADDR((small_offset << 2));
+			val = readl(TO_PMAP_ADDR(hdmitx_addr));
+		}
+		break;
 	}
 	return val;
 }
@@ -393,14 +407,27 @@ void hdmitx_wr_reg_g12a(unsigned int addr, unsigned int data)
 	unsigned int small_offset = addr & ((1 << 24)  - 1);
 	unsigned long hdmitx_addr = 0;

-	if (large_offset == 0x10) {
+	switch (large_offset) {
+	case 0x10:
+		/*DWC*/
 		hdmitx_addr = HDMITX_SEC_REG_ADDR(small_offset);
 		writeb(data & 0xff, TO_PMAP_ADDR(hdmitx_addr));
-	} else if ((large_offset == 0x11) || (large_offset == 0x01))
+		break;
+	case 0x11:
+	case 0x01:
+		/*SECURITY DWC/TOP*/
 		hdmitx_wr_reg_normal(addr, data);
-	else {
-		hdmitx_addr = HDMITX_REG_ADDR(small_offset);
-		writel(data, TO_PMAP_ADDR(hdmitx_addr));
+		break;
+	case 00:
+	default:
+		/*TOP*/
+		if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+			hdmitx_addr = HDMITX_REG_ADDR(small_offset);
+			writeb(data & 0xff, TO_PMAP_ADDR(hdmitx_addr));
+		} else {
+			hdmitx_addr = HDMITX_REG_ADDR((small_offset << 2));
+			writel(data, TO_PMAP_ADDR(hdmitx_addr));
+		}
 	}
 }

--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.h
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/reg_ops.h
@@ -72,7 +72,7 @@ struct reg_map {
 #define HDMITX_SEC_REG_ADDR(reg) \
 	((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + reg)/*DWC*/
 #define HDMITX_REG_ADDR(reg) \
-	((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg << 2))/*TOP*/
+	((HDMITX_REG_IDX << BASE_REG_OFFSET) + reg)/*TOP*/
 #define ELP_ESM_REG_ADDR(reg) \
 	((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + (reg << 2))