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drm/rockchip: vop: sync register define with linux 4.4

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Change-Id: I088a052319f91a3189b1c4811837c957daa56aef
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2019-07-18 10:20:19 +08:00
committed by Tao Huang
parent 7d604e646f
commit 0848de283c
2 changed files with 48 additions and 6 deletions
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53
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -53,6 +53,9 @@ static const uint32_t formats_win_full[] = {
DRM_FORMAT_NV12,
DRM_FORMAT_NV16,
DRM_FORMAT_NV24,
DRM_FORMAT_NV12_10,
DRM_FORMAT_NV16_10,
DRM_FORMAT_NV24_10,
};
static const uint32_t formats_win_lite[] = {
@@ -306,11 +309,11 @@ static const struct vop_intr rk3288_vop_intr = {
};
static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = {
.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 12),
.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13),
};
static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = {
.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 14),
.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15),
};
static const struct vop_data rk3288_vop_big = {
@@ -350,7 +353,7 @@ static const int rk3368_vop_intrs[] = {
WIN3_EMPTY_INTR,
HWC_EMPTY_INTR,
POST_BUF_EMPTY_INTR,
PWM_GEN_INTR,
FS_FIELD_INTR,
DSP_HOLD_VALID_INTR,
};
@@ -557,12 +560,14 @@ static const struct vop_csc rk3399_win2_csc = {
.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16),
.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18),
.r2r_offset = RK3399_WIN2_YUV2YUV_3X3,
.csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 22),
};
static const struct vop_csc rk3399_win3_csc = {
.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 24),
.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 26),
.r2r_offset = RK3399_WIN3_YUV2YUV_3X3,
.csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 30),
};
static const struct vop_win_data rk3399_vop_win_data[] = {
@@ -1060,7 +1065,8 @@ static const struct vop_win_phy rk3036_win0_data = {
.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
.alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
};
static const struct vop_win_phy rk3036_win1_data = {
@@ -1115,6 +1121,15 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
.hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
.hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4),
.rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
.rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
.lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26),
.lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27),
.mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28),
.mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
@@ -1330,7 +1345,8 @@ static const struct vop_win_phy rk3126_win1_data = {
.yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
.alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
};
static const struct vop_win_data rk3126_vop_win_data[] = {
@@ -1558,12 +1574,37 @@ static const struct vop_ctrl rk3308_ctrl_data = {
0xffffffff, 0),
};
static const int rk3308_vop_intrs[] = {
FS_INTR,
FS_NEW_INTR,
ADDR_SAME_INTR,
LINE_FLAG_INTR,
LINE_FLAG1_INTR,
BUS_ERROR_INTR,
0,
0,
DSP_HOLD_VALID_INTR,
DMA_FINISH_INTR,
0,
POST_BUF_EMPTY_INTR
};
static const struct vop_intr rk3308_vop_intr = {
.intrs = rk3308_vop_intrs,
.nintrs = ARRAY_SIZE(rk3308_vop_intrs),
.line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
.line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
.status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
.enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
.clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
};
static const struct vop_data rk3308_vop = {
.version = VOP_VERSION(2, 7),
.max_input = {1920, 8192},
.max_output = {1920, 1080},
.ctrl = &rk3308_ctrl_data,
.intr = &rk3366_lit_intr,
.intr = &rk3308_vop_intr,
.win = rk3366_vop_lit_win_data,
.win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
};

1
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -860,6 +860,7 @@
#define RK3036_SYS_CTRL 0x00
#define RK3036_DSP_CTRL0 0x04
#define RK3036_DSP_CTRL1 0x08
#define RK3036_INT_SCALER 0x0c
#define RK3036_INT_STATUS 0x10
#define RK3036_ALPHA_CTRL 0x14
#define RK3036_WIN0_COLOR_KEY 0x18