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decoder: fixed some vp9 avs2 8k problem [1/1]
PD#SWPL-2971 Problem: 1. some vp9 8k video display abnormal. 2. avs2 consume mem excessive and mosaic and crash when play avs2 8192x4608 bitdepth 10 bitstream. Solution: 1. NorthernItaly8k.mkv is 7968x3984, need set blkmod 64x32(mem_map_mode 2) for 64 aligned; 2. a special 8192x4608 bitstream which tile_x less than 15 need work around; 3. make avs2 mem consume fit with resolution and fixed crash when max resolution with 10bit. ucode gerrit id: 57342 Verify: verify on x301. Change-Id: I9da01e691e96d93bc6a120ed2fde0aa6dac52021 Signed-off-by: shihong.zheng <shihong.zheng@amlogic.com>
This commit is contained in:
committed by
Dongjin Kim
parent
255c70cc9d
commit
0879ec59c1
@@ -326,20 +326,6 @@ static const char * const video_format_names[] = {
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"MAC", "unspecified", "Reserved", "Reserved"
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};
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#define PROB_SIZE (496 * 2 * 4)
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#define PROB_BUF_SIZE (0x5000)
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#define COUNT_BUF_SIZE (0x300 * 4 * 4)
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/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
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#define MAX_FRAME_4K_NUM 0x1200
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#define MAX_FRAME_8K_NUM 0x4800
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//#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
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static int get_frame_mmu_map_size(void)
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{
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if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
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return (MAX_FRAME_8K_NUM * 4);
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return (MAX_FRAME_4K_NUM * 4);
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}
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static inline int div_r32(int64_t m, int n)
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{
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/*
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@@ -802,12 +788,31 @@ static int avs2_print_cont(struct AVS2Decoder_s *dec,
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return 0;
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}
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static int get_compress_header_size(void)
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#define PROB_SIZE (496 * 2 * 4)
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#define PROB_BUF_SIZE (0x5000)
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#define COUNT_BUF_SIZE (0x300 * 4 * 4)
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/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
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#define MAX_FRAME_4K_NUM 0x1200
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#define MAX_FRAME_8K_NUM 0x4800
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#define MAX_SIZE_4K (4096 * 2304)
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#define IS_8K_SIZE(w, h) (((w) * (h)) > MAX_SIZE_4K)
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static int get_frame_mmu_map_size(struct AVS2Decoder_s *dec)
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{
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if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
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if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) &&
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(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
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return (MAX_FRAME_8K_NUM * 4);
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return (MAX_FRAME_4K_NUM * 4);
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}
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static int get_compress_header_size(struct AVS2Decoder_s *dec)
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{
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if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) &&
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(IS_8K_SIZE(dec->init_pic_w, dec->init_pic_h)))
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return MMU_COMPRESS_8K_HEADER_SIZE;
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return MMU_COMPRESS_HEADER_SIZE;
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}
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static void reset_process_time(struct AVS2Decoder_s *dec)
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{
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if (dec->start_process_time) {
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@@ -1580,10 +1585,12 @@ static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
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.mmu_vbh = {
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.buf_size = 0x5000 * 2, /*2*16*2304/4, 4K*/
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},
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#if 0
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.cm_header = {
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/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/
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.buf_size = MMU_COMPRESS_8K_HEADER_SIZE * 17,
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},
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#endif
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#endif
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.mpred_above = {
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.buf_size = 0x8000 * 2,
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@@ -1591,7 +1598,7 @@ static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
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#ifdef MV_USE_FIXED_BUF
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.mpred_mv = {
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/*4k2k , 0x100000 per buffer*/
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.buf_size = 0x100000 * 16 * 4,
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.buf_size = 0x120000 * FRAME_BUFFERS * 4,
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},
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#endif
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.rpm = {
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@@ -2148,7 +2155,7 @@ static void init_pic_list(struct AVS2Decoder_s *dec,
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/*alloc AVS2 compress header first*/
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if (decoder_bmmu_box_alloc_buf_phy
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(dec->bmmu_box,
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HEADER_BUFFER_IDX(-1), get_compress_header_size(),
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HEADER_BUFFER_IDX(-1), get_compress_header_size(dec),
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DRIVER_HEADER_NAME,
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&buf_addr1) < 0){
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avs2_print(dec, 0,
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@@ -2162,7 +2169,7 @@ static void init_pic_list(struct AVS2Decoder_s *dec,
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unsigned long buf_addr;
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if (decoder_bmmu_box_alloc_buf_phy
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(dec->bmmu_box,
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HEADER_BUFFER_IDX(i), get_compress_header_size(),
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HEADER_BUFFER_IDX(i), get_compress_header_size(dec),
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DRIVER_HEADER_NAME,
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&buf_addr) < 0){
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avs2_print(dec, 0,
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@@ -2455,7 +2462,7 @@ static int config_mc_buffer(struct AVS2Decoder_s *dec)
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}
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return 0;
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}
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#if 0
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static void mcrcc_get_hitrate(void)
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{
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u32 tmp;
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@@ -2554,8 +2561,9 @@ static void decomp_get_hitrate(void)
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}
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if (raw_mcr_cnt != 0) {
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hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
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pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
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} else {
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if (debug & AVS2_DBG_CACHE)
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pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
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} else if (debug & AVS2_DBG_CACHE) {
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pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
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}
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return;
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@@ -2587,12 +2595,12 @@ static void decomp_get_comprate(void)
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/ raw_ucomp_cnt) * 100;
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if (debug & AVS2_DBG_CACHE)
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pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
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} else {
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if (debug & AVS2_DBG_CACHE)
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} else if (debug & AVS2_DBG_CACHE) {
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pr_info("DECOMP_COMP_RATIO : na\n");
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}
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return;
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}
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#endif
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static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
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{
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@@ -2607,13 +2615,13 @@ static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
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WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0);
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return;
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}
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/*
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if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
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mcrcc_get_hitrate();
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decomp_get_hitrate();
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decomp_get_comprate();
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}
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*/
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if ((avs2_dec->img.type == B_IMG) ||
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(avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/
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/*Programme canvas0 */
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@@ -3679,7 +3687,7 @@ static void avs2_local_uninit(struct AVS2Decoder_s *dec)
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if (dec->frame_mmu_map_addr) {
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if (dec->frame_mmu_map_phy_addr)
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dma_free_coherent(amports_get_dma_device(),
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get_frame_mmu_map_size(), dec->frame_mmu_map_addr,
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get_frame_mmu_map_size(dec), dec->frame_mmu_map_addr,
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dec->frame_mmu_map_phy_addr);
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dec->frame_mmu_map_addr = NULL;
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}
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@@ -3738,11 +3746,9 @@ static int avs2_local_init(struct AVS2Decoder_s *dec)
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&& (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
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buf_alloc_width = 1920;
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buf_alloc_height = 1088;
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} else {
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if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
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buf_alloc_width = 8192;
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buf_alloc_height = 4608;
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}
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} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
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buf_alloc_width = 8192;
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buf_alloc_height = 4608;
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}
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dec->init_pic_w = buf_alloc_width ? buf_alloc_width :
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(dec->vavs2_amstream_dec_info.width ?
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@@ -3823,13 +3829,13 @@ static int avs2_local_init(struct AVS2Decoder_s *dec)
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#ifdef AVS2_10B_MMU
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dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(),
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get_frame_mmu_map_size(),
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get_frame_mmu_map_size(dec),
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&dec->frame_mmu_map_phy_addr, GFP_KERNEL);
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if (dec->frame_mmu_map_addr == NULL) {
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pr_err("%s: failed to alloc count_buffer\n", __func__);
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return -1;
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}
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memset(dec->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
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memset(dec->frame_mmu_map_addr, 0, get_frame_mmu_map_size(dec));
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/* dec->frame_mmu_map_phy_addr = dma_map_single(amports_get_dma_device(),
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dec->frame_mmu_map_addr, FRAME_MMU_MAP_SIZE, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(amports_get_dma_device(),
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@@ -152,7 +152,6 @@ int decoder_mmu_box_alloc_idx(
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for (i = 0; i < num_pages; i++)
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mmu_index_adr[i] = PAGE_INDEX(sc->pages_list[i]);
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mmu_index_adr[num_pages] = 0;
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mutex_unlock(&box->mutex);
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@@ -304,12 +304,6 @@ struct MVBUF_s {
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/*#define ENABLE_SWAP_TEST*/
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#define MCRCC_ENABLE
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#ifdef VP9_10B_NV21
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#define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/
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#else
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#define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/
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#endif
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#define VP9_LPF_LVL_UPDATE
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/*#define DBG_LF_PRINT*/
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@@ -2668,8 +2662,11 @@ union param_u vp9_param;
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#define LOSLESS_COMPRESS_MODE
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/*#define DECOMP_HEADR_SURGENT*/
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#ifdef VP9_10B_NV21
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static u32 mem_map_mode = 2 /* 0:linear 1:32x32 2:64x32*/
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#else
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static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */
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#endif
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static u32 enable_mem_saving = 1;
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static u32 force_w_h;
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@@ -5059,7 +5056,7 @@ static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
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data32 = READ_VREG(HEVC_SAO_CTRL1);
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data32 &= (~0x3000);
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/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
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data32 |= (MEM_MAP_MODE << 12);
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data32 |= (mem_map_mode << 12);
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data32 &= (~0x3);
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data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/
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WRITE_VREG(HEVC_SAO_CTRL1, data32);
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@@ -5073,14 +5070,14 @@ static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
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data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
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data32 &= (~0x30);
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/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
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data32 |= (MEM_MAP_MODE << 4);
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data32 |= (mem_map_mode << 4);
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WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
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#else
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/*m8baby test1902*/
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data32 = READ_VREG(HEVC_SAO_CTRL1);
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data32 &= (~0x3000);
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/*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/
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data32 |= (MEM_MAP_MODE << 12);
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data32 |= (mem_map_mode << 12);
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data32 &= (~0xff0);
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/*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/
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data32 |= 0x880; /*.Big-Endian per 64-bit */
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@@ -5098,7 +5095,7 @@ static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
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data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG);
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data32 &= (~0x30);
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/*[5:4] address_format 00:linear 01:32x32 10:64x32*/
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data32 |= (MEM_MAP_MODE << 4);
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data32 |= (mem_map_mode << 4);
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data32 &= (~0xF);
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data32 |= 0x8; /*Big-Endian per 64-bit*/
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WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32);
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@@ -5106,7 +5103,7 @@ static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
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#else
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data32 = READ_VREG(HEVC_SAO_CTRL1);
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data32 &= (~0x3000);
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data32 |= (MEM_MAP_MODE <<
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data32 |= (mem_map_mode <<
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12);
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/* [13:12] axi_aformat, 0-Linear,
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@@ -6111,7 +6108,7 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
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if (vdec_is_support_4k()) {
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if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
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memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 4k */
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memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 8k */
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sizeof(struct BuffInfo_s));
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} else
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memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
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@@ -6161,6 +6158,13 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
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(pbi->vvp9_amstream_dec_info.height ?
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pbi->vvp9_amstream_dec_info.height :
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pbi->work_space_buf->max_height));
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if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) &&
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(pbi->double_write_mode != 0) &&
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(((pbi->max_pic_w % 64) != 0) ||
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(pbi->vvp9_amstream_dec_info.width % 64) != 0))
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mem_map_mode = 2;
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#ifndef MV_USE_FIXED_BUF
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if (init_mv_buf_list(pbi) < 0) {
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pr_err("%s: init_mv_buf_list fail\n", __func__);
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