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soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

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[ Upstream commit 756344e7cb ]

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Yang Yingliang
2022-10-18 10:31:48 +08:00
committed by Greg Kroah-Hartman
parent 7ea9128d1a
commit 0883dc428c
1 changed files with 4 additions and 1 deletions
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5
drivers/soc/sifive/sifive_ccache.c
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@@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
NULL);
if (rc) {
pr_err("Could not request IRQ %d\n", g_irq[i]);
goto err_unmap;
goto err_free_irq;
}
}
@@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
#endif
return 0;
err_free_irq:
while (--i >= 0)
free_irq(g_irq[i], NULL);
err_unmap:
iounmap(ccache_base);
return rc;