shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: px30 vop: add win layer selete

Browse Source 
Change-Id: I7c4b63bf39266c91087fe493e0fa63d43093fadd
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2018-01-23 20:41:06 +08:00
committed by Tao Huang
parent e222d0efb0
commit 08bfd4ef4e
1 changed files with 76 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1336,33 +1336,6 @@ static const struct vop_ctrl rk3366_lit_ctrl_data = {
.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
.afbdc_en = VOP_REG_VER(PX30_AFBCD0_CTRL, 0x1, 0, 2, 6, -1),
.afbdc_format = VOP_REG_VER(PX30_AFBCD0_CTRL, 0xf, 4, 2, 6, -1),
.afbdc_pic_vir_width = VOP_REG_VER(PX30_AFBCD0_CTRL, 0xffff,
16, 2, 6, -1),
.afbdc_hdr_ptr = VOP_REG_VER(PX30_AFBCD0_HDR_PTR, 0xffffffff,
0, 2, 6, -1),
.afbdc_pic_size = VOP_REG_VER(PX30_AFBCD0_PIC_SIZE, 0xffffffff,
0, 2, 6, -1),
.afbdc_pic_offset = VOP_REG_VER(PX30_AFBCD0_PIC_OFFSET, 0xffffffff,
0, 2, 6, -1),
.afbdc_axi_ctrl = VOP_REG_VER(PX30_AFBCD0_AXI_CTRL, 0xffffffff,
0, 2, 6, -1),
.cabc_config_mode = VOP_REG_VER(PX30_CABC_CTRL0, 0x3, 1, 2, 6, -1),
.cabc_calc_pixel_num = VOP_REG_VER(PX30_CABC_CTRL0, 0x7fffff, 4,
2, 6, -1),
.cabc_handle_en = VOP_REG_VER(PX30_CABC_CTRL0, 0x1, 3, 2, 6, -1),
.cabc_en = VOP_REG_VER(PX30_CABC_CTRL0, 0x1, 0, 2, 6, -1),
.cabc_total_num = VOP_REG_VER(PX30_CABC_CTRL1, 0x7fffff, 4, 2, 6, -1),
.cabc_lut_en = VOP_REG_VER(PX30_CABC_CTRL1, 0x1, 0, 2, 6, -1),
.cabc_stage_up_mode = VOP_REG_VER(PX30_CABC_CTRL2, 0x1, 19, 2, 6, -1),
.cabc_stage_up = VOP_REG_VER(PX30_CABC_CTRL2, 0x1ff, 8, 2, 6, -1),
.cabc_stage_down = VOP_REG_VER(PX30_CABC_CTRL2, 0xff, 0, 2, 6, -1),
.cabc_global_dn = VOP_REG_VER(PX30_CABC_CTRL3, 0xff, 0, 2, 6, -1),
.cabc_global_dn_limit_en = VOP_REG_VER(PX30_CABC_CTRL3, 0x1, 8,
2, 6, -1),
};
static const struct vop_data rk3366_vop_lit = {
@@ -1410,6 +1383,80 @@ static const struct vop_data rk3126_vop = {
* but RK3368 win2 register offset is 0xb0 and px30 is 0x190,
* so we set the PX30 VOPB win2 base = 0x190 - 0xb0 = 0xe0
*/
static const struct vop_ctrl px30_ctrl_data = {
.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
.hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
.hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
.lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
.lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
.afbdc_en = VOP_REG(PX30_AFBCD0_CTRL, 0x1, 0),
.afbdc_format = VOP_REG(PX30_AFBCD0_CTRL, 0xf, 4),
.afbdc_pic_vir_width = VOP_REG(PX30_AFBCD0_CTRL, 0xffff, 16),
.afbdc_hdr_ptr = VOP_REG(PX30_AFBCD0_HDR_PTR, 0xffffffff, 0),
.afbdc_pic_size = VOP_REG(PX30_AFBCD0_PIC_SIZE, 0xffffffff, 0),
.afbdc_pic_offset = VOP_REG(PX30_AFBCD0_PIC_OFFSET, 0xffffffff, 0),
.afbdc_axi_ctrl = VOP_REG(PX30_AFBCD0_AXI_CTRL, 0xffffffff, 0),
.cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2),
.cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4),
.cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1),
.cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0),
.cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4),
.cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0),
.cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19),
.cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8),
.cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0),
.cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0),
.cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8),
};
static const struct vop_win_data px30_vop_big_win_data[] = {
{ .base = 0x00, .phy = &rk3366_lit_win0_data,
.type = DRM_PLANE_TYPE_PRIMARY },
@@ -1433,7 +1480,7 @@ static const struct vop_data px30_vop_lit = {
.version = VOP_VERSION(2, 5),
.max_input = {1920, 8192},
.max_output = {1920, 1080},
.ctrl = &rk3366_lit_ctrl_data,
.ctrl = &px30_ctrl_data,
.intr = &rk3366_lit_intr,
.win = px30_vop_lit_win_data,
.win_size = ARRAY_SIZE(px30_vop_lit_win_data),
@@ -1444,7 +1491,7 @@ static const struct vop_data px30_vop_big = {
.feature = VOP_FEATURE_AFBDC,
.max_input = {1920, 8192},
.max_output = {1920, 1080},
.ctrl = &rk3366_lit_ctrl_data,
.ctrl = &px30_ctrl_data,
.intr = &rk3366_lit_intr,
.win = px30_vop_big_win_data,
.win_size = ARRAY_SIZE(px30_vop_big_win_data),