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arm64: dts: rockchip: rk3588-evb1: add rk3588 evb1 rk628 hdmi2csi config

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Change-Id: Id4be886b25a9097b24a1b225db208eb4b727bbff
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
This commit is contained in:
Jianwei Fan
2023-09-16 08:13:51 +00:00
committed by 范建威
parent c9885c773d
commit 08d68a6729
2 changed files with 265 additions and 0 deletions
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1
arch/arm64/boot/dts/rockchip/Makefile
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@@ -204,6 +204,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-ipc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxe.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-rk628-hdmi2csi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp2dp.dtb

264
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts Normal file
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@@ -0,0 +1,264 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3588-evb1-lp4.dtsi"
#include "rk3588-android.dtsi"
/ {
model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK628 HDMI to MIPI Extboard";
compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588";
vcc_mipicsi0: vcc-mipicsi0-regulator {
/delete-property/ gpio;
/delete-property/ pinctrl-0;
};
vcc_mipicsi1: vcc-mipicsi1-regulator {
/delete-property/ gpio;
/delete-property/ pinctrl-0;
};
vcc_mipidcphy0: vcc-mipidcphy0-regulator {
/delete-property/ gpio;
/delete-property/ pinctrl-0;
};
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_mipi2_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmiin_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_mipi0_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmiin_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c3 {
status = "okay";
rk628_csi_1: rk628_csi_1@50 {
reg = <0x50>;
compatible = "rockchip,rk628-csi-v4l2";
status = "okay";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&rk628_pin_1>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
continues-clk = <1>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HDMI-MIPI2";
rockchip,camera-module-lens-name = "RK628-CSI";
port {
hdmiin_out1: endpoint {
remote-endpoint = <&hdmi_mipi2_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c5 {
status = "okay";
rk628_csi: rk628_csi@50 {
reg = <0x50>;
compatible = "rockchip,rk628-csi-v4l2";
status = "okay";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&rk628_pin>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
continues-clk = <1>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HDMI-MIPI";
rockchip,camera-module-lens-name = "RK628-CSI";
port {
hdmiin_out0: endpoint {
remote-endpoint = <&hdmi_mipi0_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
hdmiin {
rk628_pin: rk628-pin {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
<2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
rk628_pin_1: rk628-pin-1 {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};