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phy: rockchip: naneng-combphy: select pipe to controller for rk3568

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RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connection. This patch select the pipe to the corresponding
controller when set phy mode.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Change-Id: I6ec6dd0a0202119633e594c9a72f361156330b06
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2020-11-11 15:50:30 +08:00
committed by Tao Huang
parent 3e58c5e6ae
commit 096abe6464
1 changed files with 8 additions and 0 deletions
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8
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -39,6 +39,9 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg pipe_txcomp_set;
struct combphy_reg pipe_txelec_sel;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_sel_usb;
struct combphy_reg pipe_sel_sata;
struct combphy_reg pipe_sel_qsgmii;
};
struct rockchip_combphy_priv {
@@ -88,11 +91,13 @@ static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
param_write(priv->phy_grf, &cfg->pcie_mode_set, true);
break;
case PHY_TYPE_USB3:
param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
break;
case PHY_TYPE_SATA:
param_write(priv->phy_grf, &cfg->pipe_sel_sata, true);
param_write(priv->phy_grf, &cfg->sata_mode_set, true);
break;
default:
@@ -212,6 +217,9 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_cfgs = {
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
.pipe_sel_sata = { 0x000c, 14, 13, 0x00, 0x02 },
.pipe_sel_qsgmii = { 0x000c, 14, 13, 0x00, 0x03 },
};
static const struct of_device_id rockchip_combphy_of_match[] = {