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drm/rockchip: vop: slit dither register field definitions

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Change-Id: Id6fb68b88641839fa66c01eda980e07b4317b435
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-03-26 14:51:28 +08:00
committed by Tao Huang
parent 2bb9ec21ad
commit 09866a1911
3 changed files with 45 additions and 30 deletions
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26
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -2357,32 +2357,34 @@ static void vop_update_csc(struct drm_crtc *crtc)
switch (s->bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
VOP_CTRL_SET(vop, dither_down_en, 1);
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
break;
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
VOP_CTRL_SET(vop, dither_down_en, 1);
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
break;
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
VOP_CTRL_SET(vop, dither_down_en, 0);
VOP_CTRL_SET(vop, pre_dither_down_en, 1);
break;
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
VOP_CTRL_SET(vop, dither_down_en, 0);
VOP_CTRL_SET(vop, pre_dither_down_en, 0);
break;
case MEDIA_BUS_FMT_RGB888_1X24:
default:
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
VOP_CTRL_SET(vop, dither_down_en, 0);
VOP_CTRL_SET(vop, pre_dither_down_en, 0);
break;
}
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
val |= PRE_DITHER_DOWN_EN(0);
else
val |= PRE_DITHER_DOWN_EN(1);
val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
VOP_CTRL_SET(vop, dither_down, val);
VOP_CTRL_SET(vop, pre_dither_down_en,
s->output_mode == ROCKCHIP_OUT_MODE_AAAA ? 0 : 1);
VOP_CTRL_SET(vop, dither_down_sel, DITHER_DOWN_ALLEGRO);
VOP_CTRL_SET(vop, dclk_ddr,
s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
@@ -2539,7 +2541,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
VOP_CTRL_SET(vop, hdmi_pin_pol, val);
VOP_CTRL_SET(vop, sw_genlock, 1);
VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
VOP_CTRL_SET(vop, dither_up, 1);
VOP_CTRL_SET(vop, dither_up_en, 1);
break;
default:
DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);

12
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -148,8 +148,11 @@ struct vop_ctrl {
struct vop_reg mipi_pin_pol;
struct vop_reg dp_dclk_pol;
struct vop_reg dp_pin_pol;
struct vop_reg dither_up;
struct vop_reg dither_down;
struct vop_reg dither_down_sel;
struct vop_reg dither_down_mode;
struct vop_reg dither_down_en;
struct vop_reg pre_dither_down_en;
struct vop_reg dither_up_en;
struct vop_reg sw_dac_sel;
struct vop_reg tve_sw_mode;
@@ -593,11 +596,6 @@ enum dither_down_mode_sel {
DITHER_DOWN_FRC = 0x1
};
#define PRE_DITHER_DOWN_EN(x) ((x) << 0)
#define DITHER_DOWN_EN(x) ((x) << 1)
#define DITHER_DOWN_MODE(x) ((x) << 2)
#define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
enum vop_pol {
HSYNC_POSITIVE = 0,
VSYNC_POSITIVE = 1,

37
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -225,8 +225,11 @@ static const struct vop_ctrl rk3288_ctrl_data = {
.mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
.dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
.dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
.pre_dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
.dither_up_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
@@ -925,8 +928,11 @@ static const struct vop_ctrl rk3328_ctrl_data = {
.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
.dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
.dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
.dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
.dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
.pre_dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
.dither_up_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
.dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
@@ -1104,7 +1110,10 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
.dither_down = VOP_REG(RK3036_DSP_CTRL0, 0x3, 10),
.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
.dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
@@ -1339,8 +1348,10 @@ static const struct vop_ctrl rk3366_lit_ctrl_data = {
.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
@@ -1440,8 +1451,10 @@ static const struct vop_ctrl px30_ctrl_data = {
.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
@@ -1576,8 +1589,10 @@ static const struct vop_ctrl rk3308_ctrl_data = {
.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),