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osd: add fb3 viu2 support for direct render

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PD#169796: osd: add fb3 viu2 support for direct render

Change-Id: Ic3492a5f0c26d5d517791c79c4579109f7258682
Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
This commit is contained in:
pengcheng chen
2018-07-11 16:37:54 +08:00
committed by Jianxin Pan
parent 96e7519870
commit 09a6a4bc18
3 changed files with 105 additions and 7 deletions
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8
drivers/amlogic/media/osd/osd.h
View File

@@ -152,6 +152,8 @@ enum color_index_e {
#define OSD_FREESCALE (1 << 2)
#define OSD_UBOOT_LOGO (1 << 3)
#define OSD_ZORDER (1 << 4)
#define OSD_VIU2 (1 << 29)
#define OSD_VIU1 (1 << 30)
#define OSD_LAYER_ENABLE (1 << 31)
#define BYPASS_DIN (1 << 7)
@@ -353,6 +355,11 @@ enum viu2_rotate_format {
RGBA = 8,
};
enum viu_type {
VIU1,
VIU2,
};
struct pandata_s {
s32 x_start;
s32 x_end;
@@ -737,6 +744,7 @@ struct hw_para_s {
u32 basic_urgent;
u32 two_ports;
u32 afbc_err_cnt;
u32 viu_type;
struct hw_debug_s osd_debug;
int out_fence_fd;
int in_fd[HW_OSD_COUNT];

88
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -331,6 +331,7 @@ static void osd_pan_display_single_fence(
static void osd_pan_display_layers_fence(
struct osd_layers_fence_map_s *fence_map);
static void *osd_timeline_create(void)
{
const char *tlName = "osd_timeline";
@@ -582,6 +583,53 @@ struct osd_f2v_vphase_s {
u16 phase;
};
#define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2))
#define MATRIX_5x3_COEF_SIZE 24
static int RGB709_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = {
0, 0, 0, /* pre offset */
COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
0, 0, 0, /* 10'/11'/12' */
0, 0, 0, /* 20'/21'/22' */
64, 512, 512, /* offset */
0, 0, 0 /* mode, right_shift, clip_en */
};
/*for G12A, set osd3 matrix(10bit) RGB2YUV*/
static void set_viu2_rgb2yuv(bool on)
{
if (osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_G12A) {
/* RGB -> 709 limit */
int *m = RGB709_to_YUV709l_coeff;
/* VPP WRAP OSD3 matrix */
osd_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET0_1,
((m[0] & 0xfff) << 16) | (m[1] & 0xfff));
osd_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET2,
m[2] & 0xfff);
osd_reg_write(VIU2_OSD1_MATRIX_COEF00_01,
((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff));
osd_reg_write(VIU2_OSD1_MATRIX_COEF02_10,
((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff));
osd_reg_write(VIU2_OSD1_MATRIX_COEF11_12,
((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff));
osd_reg_write(VIU2_OSD1_MATRIX_COEF20_21,
((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff));
osd_reg_write(VIU2_OSD1_MATRIX_COEF22,
m[11] & 0x1fff);
osd_reg_write(VIU2_OSD1_MATRIX_OFFSET0_1,
((m[18] & 0xfff) << 16) | (m[19] & 0xfff));
osd_reg_write(VIU2_OSD1_MATRIX_OFFSET2,
m[20] & 0xfff);
osd_reg_set_bits(VIU2_OSD1_MATRIX_EN_CTRL, on, 0, 1);
}
}
static void f2v_get_vertical_phase(
u32 zoom_ratio, enum osd_f2v_vphase_type_e type,
u8 bank_length, struct osd_f2v_vphase_s *vphase)
@@ -1055,6 +1103,10 @@ int osd_sync_request_render(u32 index, u32 yres,
osd_hw.hwc_enable = 0;
else if (request->magic == FB_SYNC_REQUEST_RENDER_MAGIC_V2)
osd_hw.hwc_enable = 1;
if (index == OSD4)
osd_hw.viu_type = VIU2;
else
osd_hw.viu_type = VIU1;
osd_hw.osd_fence[osd_hw.hwc_enable].sync_fence_handler(
index, yres, request, phys_addr);
return request->out_fen_fd;
@@ -3185,17 +3237,21 @@ int osd_get_capbility(u32 index)
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
if (index == OSD1)
capbility |= OSD_LAYER_ENABLE | OSD_FREESCALE
| OSD_UBOOT_LOGO | OSD_ZORDER;
| OSD_UBOOT_LOGO | OSD_ZORDER | OSD_VIU1;
else if ((index == OSD2) || (index == OSD3))
capbility |= OSD_LAYER_ENABLE |
OSD_VIDEO_CONFLICT | OSD_FREESCALE | OSD_ZORDER;
OSD_VIDEO_CONFLICT | OSD_FREESCALE |
OSD_ZORDER | OSD_VIU1;
else if (index == OSD4)
capbility |= OSD_LAYER_ENABLE | OSD_VIU2;
} else if (osd_hw.osd_meson_dev.osd_ver == OSD_NORMAL) {
if (index == OSD1)
capbility |= OSD_LAYER_ENABLE | OSD_FREESCALE;
capbility |= OSD_LAYER_ENABLE | OSD_FREESCALE
| OSD_VIU1;
else if (index == OSD2)
capbility |= OSD_LAYER_ENABLE |
OSD_HW_CURSOR | OSD_FREESCALE
| OSD_UBOOT_LOGO;
| OSD_UBOOT_LOGO | OSD_VIU1;
}
return capbility;
}
@@ -7350,6 +7406,19 @@ static void osd_setting_old_hwc(void)
osd_wait_vsync_hw();
}
static void osd_setting_viu2(void)
{
int index = OSD4;
osd_hw.reg[OSD_COLOR_MODE].update_func(index);
/* geometry and freescale need update with ioctl */
osd_hw.reg[DISP_GEOMETRY].update_func(index);
if (!osd_hw.osd_display_debug)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
int osd_setting_blend(void)
{
int ret;
@@ -7358,9 +7427,12 @@ int osd_setting_blend(void)
osd_setting_old_hwc();
else {
if (osd_hw.hwc_enable) {
ret = osd_setting_order();
if (ret < 0)
return -1;
if (osd_hw.viu_type == VIU1) {
ret = osd_setting_order();
if (ret < 0)
return -1;
} else if (osd_hw.viu_type == VIU2)
osd_setting_viu2();
} else
osd_setting_default_hwc();
}
@@ -8198,6 +8270,8 @@ void osd_init_viu2(void)
{
u32 idx, data32;
set_viu2_rgb2yuv(1);
osd_vpu_power_on_viu2();
/* here we will init default value ,these value only set once . */

16
drivers/amlogic/media/osd/osd_reg.h
View File

@@ -1425,4 +1425,20 @@
#define VPP_RDARB_MODE 0x3978
#define VPP_RDARB_REQEN_SLV 0x3979
#define VPU_RDARB_MODE_L2C1 0x279d
/*VIU2 osd1 reg*/
#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70
#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71
#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72
#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73
#define VIU2_OSD1_MATRIX_COEF22 0x1e74
#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75
#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76
#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77
#define VIU2_OSD1_MATRIX_CLIP 0x1e78
#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79
#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a
#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b
#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c
#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d
#endif