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https://github.com/hardkernel/linux.git
synced 2026-06-10 04:48:04 +09:00
edit system suspend vol control code
This commit is contained in:
root
@@ -179,8 +179,15 @@ config RK29_LAST_LOG
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default y
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help
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It is only intended for debugging.
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config RK29_SRAM_SPI
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tristate "Support spi driver codec run in sram"
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menu "The control interface support for RK29 suspend "
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config RK29_SPI_INSRAM
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tristate "Support spi control interface"
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depends on REGULATOR_WM831X
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default n
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config RK29_PWM_INSRAM
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tristate "Support pwm control interface"
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depends on RK29_PWM_REGULATOR
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default y
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endmenu
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endif
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@@ -9,7 +9,8 @@ obj-$(CONFIG_USB_GADGET) += usb_detect.o
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_CPU_FREQ) += cpufreq.o
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obj-$(CONFIG_RK29_VPU) += vpu.o vpu_mem.o
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obj-$(CONFIG_RK29_SRAM_SPI) += spi_sram.o
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obj-$(CONFIG_RK29_SPI_INSRAM) += spi_sram.o
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obj-$(CONFIG_RK29_PWM_INSRAM) += pwm_sram.o
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obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
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obj-$(CONFIG_MACH_RK29SDK_DDR3) += board-rk29-ddr3sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
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obj-$(CONFIG_MACH_RK29WINACCORD) += board-rk29-winaccord.o board-rk29sdk-key.o
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21
arch/arm/mach-rk29/include/mach/pm-vol.h
Normal file
21
arch/arm/mach-rk29/include/mach/pm-vol.h
Normal file
@@ -0,0 +1,21 @@
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#ifndef PM_VOL_H
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#define PM_VOL_H
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#if defined(CONFIG_RK29_SPI_INSRAM)||defined(CONFIG_RK29_PWM_INSRAM)
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void interface_ctr_reg_pread(void);
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unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol);
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void __sramfunc rk29_suspend_voltage_resume(unsigned int vol);
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#else
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#define interface_ctr_reg_pread()
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static unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
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{
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}
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#define rk29_suspend_voltage_resume(a)
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#endif
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#endif
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@@ -9,9 +9,6 @@
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#include <linux/suspend.h>
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#include <linux/random.h>
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#include <linux/crc32.h>
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#ifdef CONFIG_RK29_PWM_REGULATOR
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#include <linux/regulator/rk29-pwm-regulator.h>
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#endif
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#include <linux/io.h>
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#include <linux/wakelock.h>
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#include <asm/tlbflush.h>
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@@ -26,18 +23,8 @@
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#include <mach/gpio.h>
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#include <mach/ddr.h>
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#include <mach/memtester.h>
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#include <mach/iomux.h>
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#if defined(CONFIG_RK29_SRAM_SPI)
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void sram_spi_pread(void);
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void __sramfunc rk29_spi_ctr_vol_sleep(void);
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void __sramfunc rk29_spi_ctr_vol_resume(void);
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#else
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#define sram_spi_pread()
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#define rk29_spi_ctr_vol_sleep()
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#define rk29_spi_ctr_vol_resume()
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#endif
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#include <mach/pm-vol.h>
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#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
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#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
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@@ -151,42 +138,6 @@ static void inline printascii(const char *s) {}
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static void inline printhex(unsigned int hex) {}
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#endif /* DEBUG */
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#ifdef CONFIG_RK29_PWM_REGULATOR
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#define pwm_write_reg(addr, val) __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10))
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#define pwm_read_reg(addr) __raw_readl(addr + (RK29_PWM_BASE + 2*0x10))
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static u32 __sramdata pwm_lrc, pwm_hrc;
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static void __sramfunc rk29_set_core_voltage(int uV)
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{
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u32 gate1;
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gate1 = cru_readl(CRU_CLKGATE1_CON);
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cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
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/* iomux pwm2 */
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writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58);
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if (uV) {
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pwm_lrc = pwm_read_reg(PWM_REG_LRC);
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pwm_hrc = pwm_read_reg(PWM_REG_HRC);
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}
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pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET);
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if (uV == 1000000) {
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pwm_write_reg(PWM_REG_LRC, 12);
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pwm_write_reg(PWM_REG_HRC, 10);
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} else {
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pwm_write_reg(PWM_REG_LRC, pwm_lrc);
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pwm_write_reg(PWM_REG_HRC, pwm_hrc);
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}
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pwm_write_reg(PWM_REG_CNTR, 0);
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pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
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LOOP(5 * 1000 * LOOPS_PER_USEC); /* delay 5ms */
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cru_writel(gate1, CRU_CLKGATE1_CON);
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}
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#endif /* CONFIG_RK29_PWM_REGULATOR */
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/*volatile __sramdata */int ddr_debug;
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module_param(ddr_debug, int, 0644);
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#if 1
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@@ -277,6 +228,7 @@ void __sramfunc ddr_testmode(void)
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static void __sramfunc rk29_sram_suspend(void)
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{
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u32 clksel0;
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u32 vol;
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if ((ddr_debug == 1) || (ddr_debug == 2))
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ddr_testmode();
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@@ -285,13 +237,7 @@ static void __sramfunc rk29_sram_suspend(void)
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ddr_suspend();
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printch('6');
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#ifdef CONFIG_RK29_PWM_REGULATOR
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rk29_set_core_voltage(1000000);
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#endif
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#if defined(CONFIG_RK29_SRAM_SPI)
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rk29_spi_ctr_vol_sleep();
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#endif
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vol=rk29_suspend_voltage_set(1000000);
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printch('7');
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clksel0 = cru_readl(CRU_CLKSEL0_CON);
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/* set arm clk 24MHz/32 = 750KHz */
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@@ -306,12 +252,8 @@ static void __sramfunc rk29_sram_suspend(void)
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cru_writel(clksel0, CRU_CLKSEL0_CON);
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printch('7');
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#ifdef CONFIG_RK29_PWM_REGULATOR
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rk29_set_core_voltage(0);
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#endif
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#if defined(CONFIG_RK29_SRAM_SPI)
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rk29_spi_ctr_vol_resume();
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#endif
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rk29_suspend_voltage_resume(vol);
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printch('6');
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@@ -409,13 +351,8 @@ static int rk29_pm_enter(suspend_state_t state)
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#endif
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printch('0');
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interface_ctr_reg_pread();
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#ifdef CONFIG_RK29_PWM_REGULATOR
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/* touch TLB */
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flush_tlb_all();
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readl(RK29_PWM_BASE);
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readl(RK29_GRF_BASE);
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#endif
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/* disable clock */
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clkgate[0] = cru_readl(CRU_CLKGATE0_CON);
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@@ -486,9 +423,7 @@ static int rk29_pm_enter(suspend_state_t state)
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delay_500ns();
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/* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
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cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
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#if defined(CONFIG_RK29_SRAM_SPI)
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sram_spi_pread();
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#endif
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printch('4');
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rk29_suspend();
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84
arch/arm/mach-rk29/pwm_sram.c
Normal file
84
arch/arm/mach-rk29/pwm_sram.c
Normal file
@@ -0,0 +1,84 @@
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#include <mach/rk29_iomap.h>
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#include <mach/board.h>
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#include <mach/sram.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <mach/cru.h>
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#include <linux/regulator/rk29-pwm-regulator.h>
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#define pwm_write_reg(addr, val) __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10))
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#define pwm_read_reg(addr) __raw_readl(addr + (RK29_PWM_BASE + 2*0x10))
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#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
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#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); dsb(); } while (0)
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void interface_ctr_reg_pread(void)
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{
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flush_tlb_all();
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readl(RK29_PWM_BASE);
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readl(RK29_GRF_BASE);
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}
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static unsigned int __sramdata pwm_lrc,pwm_hrc;
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static void __sramfunc rk29_pwm_set_core_voltage(unsigned int uV)
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{
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u32 gate1;
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gate1 = cru_readl(CRU_CLKGATE1_CON);
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cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON);
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/* iomux pwm2 */
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writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58);
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if (uV) {
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pwm_lrc = pwm_read_reg(PWM_REG_LRC);
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pwm_hrc = pwm_read_reg(PWM_REG_HRC);
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}
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pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET);
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if (uV == 1000000) {
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pwm_write_reg(PWM_REG_LRC, 12);
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pwm_write_reg(PWM_REG_HRC, 10);
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} else {
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pwm_write_reg(PWM_REG_LRC, pwm_lrc);
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pwm_write_reg(PWM_REG_HRC, pwm_hrc);
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}
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pwm_write_reg(PWM_REG_CNTR, 0);
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pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
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LOOP(5 * 1000 * LOOPS_PER_USEC); /* delay 5ms */
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cru_writel(gate1, CRU_CLKGATE1_CON);
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}
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unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
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{
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rk29_pwm_set_core_voltage(1000000);
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return 0;
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}
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void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
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{
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rk29_pwm_set_core_voltage(0);
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return 0;
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}
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/*
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void interface_ctr_reg_pread(void)
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{
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}
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unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
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{
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}
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void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
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{
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}
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*/
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@@ -1,131 +1,388 @@
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#include <mach/spi_sram.h>
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#include <mach/rk29_iomap.h>
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#include <mach/board.h>
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#include <mach/sram.h>
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#include <asm/io.h>
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unsigned __sramdata int spibase;
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u32 __sramdata spi_base[2]={RK29_SPI0_BASE,RK29_SPI1_BASE};
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u32 __sramdata spi_data[6]={};
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//chcs : &0xf0->ch(spi1spi0), &ox0f->cs(cs1cs0)
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#define SPI_KHZ (1000)
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#define SPI_MHZ (1000*1000)
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#define GPLL_SPEED (24*SPI_MHZ)
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#define SPI_SR_SPEED (2*SPI_MHZ)
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void __sramfunc delay_test(int delay_time)
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#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)
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#define SRAM_SPI_CH 1
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#define SRAM_SPI_CS 1
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#define SRAM_SPI_DATA_BYTE 2
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#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
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#define SPI_SPEED (500*SPI_KHZ)
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//#elif defined()
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#else
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#define SRAM_SPI_CH 1
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#define SRAM_SPI_CS 1
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#define SRAM_SPI_DATA_BYTE 2
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#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE
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#define SPI_SPEED (500*SPI_KHZ)
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#endif
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#define SRAM_SPI_SR_DIV (GPLL_SPEED/SPI_SR_SPEED-1) //
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#define SRAM_SPI_DIV (SPI_SR_SPEED/SPI_SPEED)
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//#include <mach/spi_sram.h>
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#define SPIM_ENR 0x0008
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#define SPIM_SER 0x000C
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#define SPIM_CTRLR0 0x0000
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#define SPIM_BAUDR 0x0010
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#define SPIM_TXFTLR 0x0014
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#define SPIM_RXFLR 0x0020
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#define SPIM_SR 0x0024
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#define SPIM_IMR 0x002c
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#define SPIM_TXDR 0x400
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#define SPIM_RXDR 0x800
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/* Bit fields in rxflr, */
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#define RXFLR_MASK (0x3f)
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define CRU_CLKSEL6_CON 0x2C
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#define CRU_CLKGATE2_CON 0x64
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#define CRU_CLKGATE1_CON 0x60
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#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
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#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE + offset)
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enum
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{
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GRF_IOM50=0,
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GRF_IOM5c,
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CLKGATE1,
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CLKGATE2,
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CLKSEL6,
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SPI_CTRLR0,
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SPI_BAUDR,
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SPI_SER,
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DATE_END,
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};
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/*unsigned int __sramdata spibase;
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unsigned int __sramdata sram_spi_cs;
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u32 __sramdata spi_base[2]={RK29_SPI0_BASE,RK29_SPI1_BASE};*/
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u32 __sramdata spi_data[DATE_END]={};
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#define sram_spi_dis() spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR)
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#define sram_spi_en() spi_writel(spi_readl(SPIM_ENR)|(0x1<<0),SPIM_ENR)
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#define sram_spi_cs_dis() spi_writel(spi_readl(SPIM_SER)&~0x3,SPIM_SER)
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#define sram_spi_cs_en() spi_writel((spi_readl(SPIM_SER)&~0x3)|(0x1<<SRAM_SPI_CS),SPIM_SER);
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#define sram_spi_busy() (spi_readl(SPIM_SR)&SR_BUSY)
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#define wm831x_RD_MSK (0x1<<15)
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#define wm831x_RD_VOID (0x7FFF)
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#define spi_ctr0_mask 0x1fffc3
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#if 0
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void __sramfunc sram_printch(char byte);
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void __sramfunc sram_printHX(unsigned int hex);
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#else
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#define sram_printch(a)
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#define sram_printHX(a)
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#endif
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#define LOOPS_PER_USEC 13
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#define LOOP(loops) do { int i = loops; barrier(); while (i--) barrier(); } while (0)
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#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
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/*
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#define SRAM_ASM_LOOP_INSTRUCTION_NUM 8
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static void __sramfunc sram_udelay(unsigned long usecs, unsigned long arm_freq_mhz)
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{
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unsigned int cycle;
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cycle = usecs * arm_freq_mhz / SRAM_ASM_LOOP_INSTRUCTION_NUM;
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while (cycle--) {
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nop();
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nop();
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nop();
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barrier();
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}
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}*/
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/*void __sramfunc delay_test(int delay_time)
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{
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int n = 100 * delay_time;
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while(n--)
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{
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__asm__ __volatile__("");
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}
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}*/
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#define SPI_GATE1_MASK 0xCF
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void interface_ctr_reg_pread(void)
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{
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unsigned int temp,temp2;
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||||
|
||||
temp=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
temp2=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
|
||||
writel(temp&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
writel(temp2&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
|
||||
readl(SRAM_SPI_ADDRBASE);
|
||||
|
||||
writel(temp2,RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
writel(temp,RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
|
||||
}
|
||||
|
||||
void __sramfunc spi_reg_init(unsigned char size,unsigned char ch,unsigned char cs){
|
||||
unsigned int ret=0;
|
||||
|
||||
spibase=spi_base[ch];
|
||||
ret=readl(spibase + SPIM_ENR);
|
||||
writel(ret&~(0x1<<0), spibase + SPIM_ENR); //disable SPI reg
|
||||
|
||||
ret = readl(spibase + SPIM_SER);
|
||||
writel(ret&~(0xffffffff)|(0x1<<cs), spibase + SPIM_SER); //cs0\1
|
||||
|
||||
ret = readl(spibase + SPIM_CTRLR0);
|
||||
spi_data[5]=ret&~(1<<18)&~(1<<13)&~(1<<8)&~(0x3<<1)|(1<<11);
|
||||
writel(spi_data[5]|size,spibase + SPIM_CTRLR0); // 16\8\4 wei
|
||||
|
||||
ret=readl(spibase + SPIM_BAUDR);
|
||||
writel(ret&(~0xffff)|0x2,spibase + SPIM_BAUDR); //sout clk
|
||||
static void __sramfunc sram_spi_deinit(void)
|
||||
{
|
||||
sram_spi_dis();
|
||||
|
||||
ret=readl(spibase + SPIM_ENR);
|
||||
writel(ret|0x1, spibase + SPIM_ENR); //enable spi
|
||||
spi_writel(spi_data[SPI_CTRLR0],SPIM_CTRLR0);
|
||||
spi_writel(spi_data[SPI_BAUDR],SPIM_BAUDR);
|
||||
spi_writel(spi_data[SPI_SER],SPIM_SER);
|
||||
|
||||
}
|
||||
void __sramfunc spi_deinit(void){
|
||||
|
||||
writel(spi_data[0],RK29_GRF_BASE + 0x5c);
|
||||
writel(spi_data[1],RK29_GRF_BASE +0x50);
|
||||
writel(0, spibase + SPIM_ENR);
|
||||
writel(spi_data[2], RK29_CRU_BASE + CRU_CLKSEL6_CON);
|
||||
writel(spi_data[3],RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
writel(spi_data[4],RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
|
||||
}
|
||||
void __sramfunc spi_init( unsigned char ch,unsigned char cs){
|
||||
unsigned int ret=0;
|
||||
ret=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
spi_data[4]=ret;
|
||||
writel(ret&~(1<<3)&~(1<<2)&~(1<<1)&~(1<<0),RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
spi_data[3]=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
spi_data[0]=readl(RK29_GRF_BASE +0x5c);
|
||||
spi_data[2]=readl(RK29_CRU_BASE + CRU_CLKSEL6_CON);
|
||||
spi_data[1]=readl(RK29_GRF_BASE +0x50);
|
||||
writel(spi_data[3]&~(1<<(15+ch)),RK29_CRU_BASE + CRU_CLKGATE2_CON); //spi0\1 clk enable
|
||||
writel(spi_data[1]&~(1<<(8-2*ch))|(1<<(9-2*ch)),RK29_GRF_BASE +0x50); //sp0\1 cs1 iomux
|
||||
writel(spi_data[0]&~(1<<(3+8*ch))|(1<<(2+8*ch)),RK29_GRF_BASE +0x5c); //spi0\1 cs0 iomux
|
||||
if(ch!=0){
|
||||
writel(spi_data[2]&~(0x7f<<11)|(0x0b<<11),RK29_CRU_BASE + CRU_CLKSEL6_CON); //spi1 clk speed
|
||||
writel(spi_data[0]&~(1<<15)&~(1<<13)&~(1<<9)|(1<<14)|(1<<12)|(1<<8),RK29_GRF_BASE +0x5c); //spi1 clk\txd\rxd iomux
|
||||
}
|
||||
else{
|
||||
writel(spi_data[2]&~(0x7f<<2)|(0x0b<<2),RK29_CRU_BASE + CRU_CLKSEL6_CON); //spi0 clk speed
|
||||
writel(spi_data[0]&~(1<<7)&~(1<<5)&~(1<<1)|(1<<6)|(1<<4)|(1<<0),RK29_GRF_BASE +0x5c); //spi0 clk\txd\rxd iomux
|
||||
}
|
||||
|
||||
writel(spi_data[GRF_IOM5c],RK29_GRF_BASE + 0x5c);
|
||||
writel(spi_data[GRF_IOM50],RK29_GRF_BASE +0x50);
|
||||
|
||||
writel(spi_data[CLKSEL6], RK29_CRU_BASE + CRU_CLKSEL6_CON);
|
||||
writel(spi_data[CLKGATE2],RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
writel(spi_data[CLKGATE1],RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
}
|
||||
|
||||
static void __sramfunc spi_write(unsigned int add,unsigned int data){
|
||||
static void __sramfunc sram_spi_init(void)
|
||||
{
|
||||
|
||||
sram_printch('V');
|
||||
/***************prihp clk*******************/
|
||||
spi_data[CLKGATE1]=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
writel(spi_data[CLKGATE1]&~(SPI_GATE1_MASK),RK29_CRU_BASE + CRU_CLKGATE1_CON);
|
||||
|
||||
/***************spi sr clk speed*******************/
|
||||
spi_data[CLKSEL6]=readl(RK29_CRU_BASE + CRU_CLKSEL6_CON);
|
||||
writel((spi_data[CLKSEL6]&~(0x7f<<(2+SRAM_SPI_CH*9)))|(SRAM_SPI_SR_DIV<<(2+SRAM_SPI_CH*9)),
|
||||
RK29_CRU_BASE + CRU_CLKSEL6_CON);//spi sr clk speed
|
||||
|
||||
|
||||
/***************spi clk enable*******************/
|
||||
spi_data[CLKGATE2]=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
|
||||
writel(spi_data[CLKGATE2]&~(1<<(15+SRAM_SPI_CH)),RK29_CRU_BASE + CRU_CLKGATE2_CON);//spi clk enable
|
||||
|
||||
/***************spi iomox*******************/
|
||||
spi_data[GRF_IOM50]=readl(RK29_GRF_BASE +0x50);
|
||||
spi_data[GRF_IOM5c]=readl(RK29_GRF_BASE +0x5c);
|
||||
if(SRAM_SPI_CS)
|
||||
writel((spi_data[GRF_IOM50]&~(0x3<<(8-2*SRAM_SPI_CH)))|(0x2<<(8-2*SRAM_SPI_CH)),RK29_GRF_BASE +0x50); //spi cs1 iomux
|
||||
else
|
||||
writel((spi_data[GRF_IOM5c]&~(0x3<<(2+8*SRAM_SPI_CH)))|(0x1<<(2+8*SRAM_SPI_CH)),RK29_GRF_BASE +0x5c); //spi cs0 iomux
|
||||
|
||||
writel((spi_data[GRF_IOM5c]&~(0xf3<<(SRAM_SPI_CH*8)))
|
||||
|(0x51<<(SRAM_SPI_CH*8)),RK29_GRF_BASE +0x5c); //spi clk\txd\rxd iomux
|
||||
|
||||
|
||||
/***************spi ctr*******************/
|
||||
|
||||
//spibase=spi_base[ch];
|
||||
//sram_spi_cs=cs;
|
||||
|
||||
sram_spi_dis();// disable spi
|
||||
|
||||
spi_data[SPI_CTRLR0] = spi_readl(SPIM_CTRLR0);
|
||||
spi_writel((spi_data[SPI_CTRLR0]&~0x1fffc3)|0x1<<11|(SRAM_SPI_DATA_BYTE),SPIM_CTRLR0);//spi setting
|
||||
spi_writel((spi_data[SPIM_BAUDR]&(~0xffff))|SRAM_SPI_DIV,SPIM_BAUDR);//setting spi speed
|
||||
spi_data[SPI_SER]=spi_readl(SPIM_SER);//spi cs
|
||||
|
||||
}
|
||||
|
||||
static void __sramfunc sram_spi_write(unsigned short add,unsigned short data){
|
||||
unsigned int ret=0;
|
||||
spi_reg_init(2,1,1);
|
||||
writel(add, spibase + SPIM_TXDR);
|
||||
delay_test(100);
|
||||
writel(data, spibase + SPIM_TXDR);
|
||||
delay_test(100);
|
||||
ret = readl(spibase + SPIM_SER);
|
||||
writel(ret&~(0xffffffff), spibase + SPIM_SER);
|
||||
|
||||
sram_spi_cs_en();
|
||||
sram_udelay(10,24);
|
||||
sram_spi_en();
|
||||
|
||||
spi_writel(add,SPIM_TXDR);
|
||||
spi_writel(data,SPIM_TXDR);
|
||||
//delay_test(100);
|
||||
|
||||
sram_udelay(100,24);
|
||||
|
||||
while(sram_spi_busy())
|
||||
{
|
||||
sram_udelay(1,24);
|
||||
sram_printch('B');
|
||||
}
|
||||
|
||||
sram_spi_dis();
|
||||
sram_udelay(10,24);
|
||||
sram_spi_cs_dis();
|
||||
}
|
||||
static unsigned int __sramfunc spi_read(unsigned int add,unsigned int data){
|
||||
unsigned int ret=0,ret1=0;
|
||||
spi_reg_init(2,1,1);
|
||||
writel(add, spibase + SPIM_TXDR);
|
||||
delay_test(100);
|
||||
writel(data, spibase + SPIM_TXDR);
|
||||
delay_test(100);
|
||||
ret=readl(spibase + SPIM_RXDR);
|
||||
//printhex(ret);
|
||||
//printch('\n');
|
||||
ret1=readl(spibase + SPIM_RXDR);
|
||||
//printhex(ret1);
|
||||
//printch('\n');
|
||||
return ret1;
|
||||
ret = readl(spibase + SPIM_SER);
|
||||
writel(ret&~(0xffffffff), spibase + SPIM_SER);
|
||||
static unsigned short __sramfunc sram_spi_read(unsigned short add,unsigned short data){
|
||||
unsigned short ret=-1,ret1;
|
||||
|
||||
sram_spi_cs_en();
|
||||
sram_udelay(10,24);
|
||||
sram_spi_en();
|
||||
|
||||
spi_writel(add,SPIM_TXDR);
|
||||
//delay_test(100);
|
||||
spi_writel(data,SPIM_TXDR);
|
||||
while(sram_spi_busy())
|
||||
{
|
||||
sram_udelay(1,24);
|
||||
sram_printch('B');
|
||||
}
|
||||
sram_udelay(100,24);
|
||||
|
||||
ret1=spi_readl(SPIM_RXDR);
|
||||
ret=spi_readl(SPIM_RXDR);
|
||||
|
||||
while(sram_spi_busy())
|
||||
{
|
||||
sram_udelay(1,24);
|
||||
sram_printch('B');
|
||||
}
|
||||
|
||||
sram_spi_dis();
|
||||
sram_udelay(10,24);
|
||||
sram_spi_cs_dis();
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)
|
||||
|
||||
unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
|
||||
{
|
||||
#if 1 //test
|
||||
unsigned short addr_4003=0x4003,addr_405d=0x405d,
|
||||
addr_4059=0x4059,addr_405e=0x405e,addr_4063=0x4063;
|
||||
unsigned short data_4003,data_405d,
|
||||
data_405e,data_4059,data_4063;
|
||||
|
||||
sram_printch('s');
|
||||
sram_spi_init();
|
||||
sram_printch('\n');
|
||||
sram_printch('M');
|
||||
data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4059);//dc1 sleep
|
||||
|
||||
data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_405e);//dc2 sleep
|
||||
|
||||
data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_405e);//dc3 sleep
|
||||
|
||||
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);//sleep ctr
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
sram_printch('N');
|
||||
|
||||
data_4059=(data_4059&~(0x7f))|0x68;
|
||||
sram_spi_write(addr_4059,data_4059);//dc1 sleep 3.0v
|
||||
|
||||
data_405e=(data_405e&~(0x7f))|0x28;//1.2 0x38 / 1.0 0x28,1.3 0x40
|
||||
sram_spi_write(addr_405e,data_405e);//dc2 sleep
|
||||
|
||||
data_4063=(data_4063&~(0x7f))|0x56;
|
||||
sram_spi_write(addr_4063,data_4063);//dc3 sleep 1.8V
|
||||
|
||||
|
||||
|
||||
sram_printch('J');
|
||||
data_4003|=(0x1<<14);
|
||||
sram_spi_write(addr_4003,data_4003);// sleep
|
||||
|
||||
sram_printch('L');
|
||||
data_4059=sram_spi_read(addr_4059|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4059);
|
||||
|
||||
data_405e=sram_spi_read(addr_405e|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_405e);
|
||||
|
||||
|
||||
data_4063=sram_spi_read(addr_4063|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4063);
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);
|
||||
|
||||
|
||||
|
||||
sram_spi_deinit();
|
||||
#else
|
||||
unsigned short addr_4003=0x4003;
|
||||
unsigned short data_4003;
|
||||
sram_spi_init(); //iomux clk
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);//sleep ctr
|
||||
|
||||
sram_printch('G');
|
||||
data_4003|=(0x1<<14);
|
||||
sram_spi_write(addr_4003,data_4003);// sleep
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);//sleep ctr
|
||||
sram_spi_deinit();
|
||||
#endif
|
||||
}
|
||||
void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
|
||||
{
|
||||
|
||||
unsigned short addr_4003=0x4003;
|
||||
unsigned short data_4003;
|
||||
sram_spi_init(); //iomux clk
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);//sleep ctr
|
||||
|
||||
sram_printch('G');
|
||||
data_4003&=~(0x1<<14);
|
||||
sram_spi_write(addr_4003,data_4003);// sleep
|
||||
|
||||
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
|
||||
sram_printHX(data_4003);//sleep ctr
|
||||
|
||||
|
||||
sram_spi_deinit();
|
||||
|
||||
}
|
||||
void __sramfunc rk29_wm831x_sleep_test(void){
|
||||
|
||||
unsigned int data2 = 0xc003, data1 = 0x4128,ret = 0;
|
||||
unsigned int addw2 = 0x4003,addw1 = 0x405d;
|
||||
unsigned int addr2= 0xc003,addr1= 0xc05d;
|
||||
unsigned int size=2,ch=1,cs=1; //DATA SIZE IS 2^(size+2) (16wei) ch0\1 is spi0\1
|
||||
//printch('\n');
|
||||
spi_init(ch,cs); //iomux clk
|
||||
spi_reg_init(2,1,1); //spi reg size, ch,cs
|
||||
spi_write(addw1,data1);
|
||||
ret=spi_read(addr1,data1);
|
||||
spi_write(addw2,data2);
|
||||
spi_deinit();
|
||||
|
||||
}
|
||||
void __sramfunc rk29_wm831x_resume_test(void){
|
||||
|
||||
unsigned int data4 = 0x8003, data3 = 0x4140,ret = 0;
|
||||
unsigned int addw4 = 0x4003,addw3 = 0x405d;
|
||||
unsigned int addr4= 0xc003,addr3= 0xc05d;
|
||||
unsigned int size=2,ch=1,cs=1;
|
||||
//printch('\n');
|
||||
spi_init(ch,cs); // clk iomux
|
||||
spi_reg_init(2,1,1); //spi reg size,ch,cs
|
||||
spi_write(addw3,data3);
|
||||
ret=spi_read(addr3,data3);
|
||||
spi_write(addw4,data4);
|
||||
spi_deinit();
|
||||
|
||||
|
||||
#else
|
||||
void interface_ctr_reg_pread(void)
|
||||
{
|
||||
}
|
||||
|
||||
unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
|
||||
{
|
||||
}
|
||||
void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user