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drm/rockchip: vop2: wait for fs by intr raw status

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Change-Id: Idda6f973e70aa1ea0146e023173829555ccaa551
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2021-03-12 09:14:39 +08:00
committed by Tao Huang
parent e616f98e1c
commit 09d4b2c521
2 changed files with 22 additions and 8 deletions
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27
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -803,20 +803,31 @@ static void vop2_wait_for_irq_handler(struct drm_crtc *crtc)
synchronize_irq(vop2->irq);
}
static void vop2_wait_for_fs_by_vcnt(struct vop2_video_port *vp, uint32_t base_vcnt)
static bool vop2_fs_raw_status_pending(struct vop2_video_port *vp)
{
struct vop2 *vop2 = vp->vop2;
uint32_t vcnt;
uint32_t offset = vp->id * 0x10;
return vop2_readl(vop2, RK3568_VP0_INT_RAW_STATUS + offset) & 0x20;
}
static void vop2_wait_for_fs_by_raw_status(struct vop2_video_port *vp)
{
struct vop2 *vop2 = vp->vop2;
bool pending;
int ret;
/*
* Spin until vcnt wraps around(from a big value to a little value)
* Spin until frame start interrupt raw status bit goes high,
* which means the configuration before the previous config done
* has take effect.
*/
ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt,
vcnt < base_vcnt, 0, 20 * 1000);
ret = readx_poll_timeout_atomic(vop2_fs_raw_status_pending, vp, pending,
pending, 0, 10 * 1000);
if (ret)
DRM_DEV_ERROR(vop2->dev, "wait fs for vp%d timeout: %d--->%d\n",
vp->id, base_vcnt, vcnt);
DRM_DEV_ERROR(vop2->dev, "wait vp%d raw fs statu timeout\n", vp->id);
}
static inline void vop2_cfg_done(struct drm_crtc *crtc)
@@ -857,7 +868,7 @@ static inline void vop2_cfg_done(struct drm_crtc *crtc)
vcnt = vop2_read_vcnt(done_vp);
/* if close to the last 1/8 frame, wait to next frame */
if (vcnt > (adjusted_mode->crtc_vtotal * 7 >> 3)) {
vop2_wait_for_fs_by_vcnt(done_vp, vcnt);
vop2_wait_for_fs_by_raw_status(done_vp);
done_bits = 0;
}
}

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1077,12 +1077,15 @@
#define RK3568_VP0_INT_EN 0xA0
#define RK3568_VP0_INT_CLR 0xA4
#define RK3568_VP0_INT_STATUS 0xA8
#define RK3568_VP0_INT_RAW_STATUS 0xAC
#define RK3568_VP1_INT_EN 0xB0
#define RK3568_VP1_INT_CLR 0xB4
#define RK3568_VP1_INT_STATUS 0xB8
#define RK3568_VP1_INT_RAW_STATUS 0xBC
#define RK3568_VP2_INT_EN 0xC0
#define RK3568_VP2_INT_CLR 0xC4
#define RK3568_VP2_INT_STATUS 0xC8
#define RK3568_VP2_INT_RAW_STATUS 0xCC
/* Video Port registers definition */
#define RK3568_VP0_DSP_CTRL 0xC00