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hdmirx: modify drop video frame interface [1/1]
PD#SWPL-6785 Problem: there's garbage frame show when signal change Solution: enable forward video frame skip interface, and set vdin to skip one more frame to prevent garbage been shown Verify: X301 Change-Id: Id099558c733843f330b99246ea31fbbd0c18ed84 Signed-off-by: Hang Cheng <hang.cheng@amlogic.com> Conflicts: drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
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@@ -258,8 +258,7 @@ static int video_onoff_state = VIDEO_ENABLE_STATE_IDLE;
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static u32 video_onoff_time;
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static DEFINE_SPINLOCK(video2_onoff_lock);
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static int video2_onoff_state = VIDEO_ENABLE_STATE_IDLE;
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static u32 hdmiin_frame_check;
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static u32 hdmiin_frame_check_cnt;
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static u32 frame_skip_check_cnt;
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/*frame_detect_flag: 1 enable, 0 disable */
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@@ -5922,7 +5921,8 @@ static inline bool video_vf_disp_mode_check(struct vframe_s *vf)
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} else
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vf_notify_provider_by_name("vdin0",
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VFRAME_EVENT_RECEIVER_DISP_MODE, (void *)&req);
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if (req.disp_mode == VFRAME_DISP_MODE_OK)
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if ((req.disp_mode == VFRAME_DISP_MODE_OK) ||
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(req.disp_mode == VFRAME_DISP_MODE_NULL))
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return false;
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/*whether need to check pts??*/
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video_vf_put(vf);
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@@ -7145,14 +7145,15 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
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* quickly for display
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*case2:input buffer all not OK
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*/
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if (vf && hdmiin_frame_check &&
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(vf->source_type == VFRAME_SOURCE_TYPE_HDMI) &&
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if (vf &&
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((vf->source_type == VFRAME_SOURCE_TYPE_HDMI) ||
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(vf->source_type == VFRAME_SOURCE_TYPE_CVBS)) &&
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(video_vf_disp_mode_get(vf) ==
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VFRAME_DISP_MODE_UNKNOWN) &&
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(hdmiin_frame_check_cnt++ < 10))
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(frame_skip_check_cnt++ < 10))
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break;
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else
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hdmiin_frame_check_cnt = 0;
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frame_skip_check_cnt = 0;
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vf = video_vf_get();
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if (!vf) {
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@@ -7170,8 +7171,9 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
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ATRACE_COUNTER(MODULE_NAME, __LINE__);
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break;
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}
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if (vf && hdmiin_frame_check && (vf->source_type ==
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VFRAME_SOURCE_TYPE_HDMI) &&
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if (vf &&
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((vf->source_type == VFRAME_SOURCE_TYPE_HDMI) ||
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(vf->source_type == VFRAME_SOURCE_TYPE_CVBS)) &&
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video_vf_disp_mode_check(vf))
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break;
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force_blackout = 0;
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@@ -13774,9 +13776,6 @@ MODULE_PARM_DESC(underflow, "\n Underflow count\n");
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module_param(next_peek_underflow, uint, 0664);
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MODULE_PARM_DESC(skip, "\n Underflow count\n");
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module_param(hdmiin_frame_check, uint, 0664);
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MODULE_PARM_DESC(hdmiin_frame_check, "\n hdmiin_frame_check\n");
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module_param(step_enable, uint, 0664);
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MODULE_PARM_DESC(step_enable, "\n step_enable\n");
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@@ -129,7 +129,7 @@ bool en_4096_2_3840;
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int en_4k_2_2k;
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int en_4k_timing = 1;
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bool hdmi_cec_en;
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int vdin_drop_frame_cnt = 1;
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int vdin_drop_frame_cnt = 2;
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/* suspend_pddq_sel:
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* 0: keep phy on when suspend(don't need phy init when
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* resume), it doesn't work now because phy VDDIO_3.3V
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@@ -34,7 +34,7 @@
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#include "hdmi_rx_edid.h"
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#define RX_VER0 "ver.2019-04-09"
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#define RX_VER0 "ver.2019-04-16"
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/*
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*
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*
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@@ -67,7 +67,8 @@ static bool phy_fsm_enhancement = true;
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static uint32_t modet_clk = 24000;
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int hdcp_enc_mode;
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/* top_irq_en bit[16:13] hdcp_sts */
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int top_intr_maskn_value = 1;
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int top_intr_maskn_value = 0x20000001;
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bool hdcp_enable = 1;
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int acr_mode;
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int auto_aclk_mute = 2;
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@@ -3347,22 +3348,22 @@ uint32_t aml_phy_pll_band(uint32_t cableclk,
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static const uint32_t phy_misci[][4] = {
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/* 0xd7 0xd8 0xe0 0xe1 */
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{ /* 24~45M */
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0x3003707f, 0x00000080, 0x02218000, 0x00000010,
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0x3007707f, 0x00000080, 0x02218000, 0x00000010,
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},
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{ /* 45~74.5M */
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0x3003707f, 0x00000080, 0x02218000, 0x00000010,
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0x3007707f, 0x00000080, 0x02218000, 0x00000010,
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},
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{ /* 77~155M */
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0x3003707f, 0x00000080, 0x02218000, 0x00000010,
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0x3007707f, 0x00000080, 0x02218000, 0x00000010,
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},
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{ /* 155~340M */
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0x3003707f, 0x00000080, 0x02218000, 0x00000010,
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0x3007707f, 0x00000080, 0x02218000, 0x00000010,
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},
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{ /* 340~525M */
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0x3003707f, 0x007f0080, 0x02218000, 0x00000010,
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0x3007707f, 0x007f0080, 0x02218000, 0x00000010,
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},
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{ /* 525~600M */
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0x3003707f, 0x007f8080, 0x02218000, 0x00000010,
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0x3007707f, 0x007f8080, 0x02218000, 0x00000010,
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},
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};
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@@ -1107,6 +1107,7 @@ extern int find_best_eq;
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extern int eq_try_cnt;
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extern int pll_rst_max;
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extern int cdr_lock_level;
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extern int top_intr_maskn_value;
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extern void rx_get_best_eq_setting(void);
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extern int hbr_force_8ch;
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extern void wr_reg_hhi(unsigned int offset, unsigned int val);
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@@ -522,10 +522,12 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
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hdmirx_wr_top(TOP_INTR_STAT_CLR, hdmirx_top_intr_stat);
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/* modify interrupt flow for isr loading */
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/* top interrupt handler */
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if (rx.chip_id == CHIP_ID_TL1) {
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if (hdmirx_top_intr_stat & (1 << 29))
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if (rx.chip_id >= CHIP_ID_TL1) {
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if (hdmirx_top_intr_stat & (1 << 29)) {
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skip_frame(skip_frame_cnt);
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if (log_level & 0x100)
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rx_pr("[isr] sqofclk_fall\n");
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}
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if (hdmirx_top_intr_stat & (1 << 28))
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if (log_level & 0x100)
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rx_pr("[isr] sqofclk_rise\n");
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@@ -1718,6 +1720,8 @@ int rx_set_global_variable(const char *buf, int size)
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return pr_var(hbr_force_8ch, index);
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if (set_pr_var(tmpbuf, cdr_lock_level, value, &index, ret))
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return pr_var(cdr_lock_level, index);
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if (set_pr_var(tmpbuf, top_intr_maskn_value, value, &index, ret))
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return pr_var(top_intr_maskn_value, index);
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return 0;
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}
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@@ -1826,6 +1830,7 @@ void rx_get_global_variable(const char *buf)
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pr_var(hdcp_enc_mode, i++);
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pr_var(hbr_force_8ch, i++);
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pr_var(cdr_lock_level, i++);
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pr_var(top_intr_maskn_value, i++);
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}
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void skip_frame(unsigned int cnt)
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@@ -1024,16 +1024,15 @@ void vdin_vf_disp_mode_update(struct vf_entry *vfe, struct vf_pool *p)
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VFRAME_DISP_MODE_OK;
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p->disp_mode[p->disp_index[0]] = VFRAME_DISP_MODE_UNKNOWN;
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}
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/*disp mode skip
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*skip_vf_num
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* 2:last last vframe, 1:last vframe
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* 0:current vframe
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/*skip all from current
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*disp_index[i]:
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*2:last last vframe, 1:last vframe
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*0:current vframe
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*/
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void vdin_vf_disp_mode_skip(struct vf_pool *p)
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{
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unsigned int i;
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for (i = p->skip_vf_num - 1; i < VFRAME_DISP_MAX_NUM; i--)
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p->disp_mode[i] = VFRAME_DISP_MODE_SKIP;
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for (i = 0; i <= p->skip_vf_num; i++)
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p->disp_mode[p->disp_index[i]] = VFRAME_DISP_MODE_SKIP;
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}
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