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spi: rockchip: Preset cs-high and clk polarity in setup progress

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After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the the first
transmission comming.

Change-Id: Ib00336a3ebda6e04bdb33c56c7da419bfb6efdd9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2021-09-22 21:03:32 +08:00
committed by Tao Huang
parent 7a48f58291
commit 0aa9fa02c4
1 changed files with 13 additions and 0 deletions
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13
drivers/spi/spi-rockchip.c
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@@ -728,6 +728,19 @@ static int rockchip_spi_setup(struct spi_device *spi)
int ret = -EINVAL;
struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
u32 cr0;
pm_runtime_get_sync(rs->dev);
cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
if (spi->mode & SPI_CS_HIGH)
cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
pm_runtime_put(rs->dev);
if (spi->cs_gpio == -ENOENT)
return 0;