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arm64: dts: rockchip: px30: Add bus_apll device node

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Change-Id: I6f2ea99e58069962bd04461b959d208c8453f42b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-05-24 10:05:42 +08:00
committed by Tao Huang
parent f0b53eb6a4
commit 0b318ea183
1 changed files with 45 additions and 22 deletions
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67
arch/arm64/boot/dts/rockchip/px30.dtsi
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@@ -203,6 +203,51 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
bus_soc: bus-soc {
compatible = "rockchip,px30-bus";
rockchip,busfreq-policy = "autocs";
soc-bus0 {
bus-id = <0>;
timer-us = <20>;
enable-msk = <0x40f7>;
};
soc-bus1 {
bus-id = <1>;
timer-us = <200>;
enable-msk = <0x40bf>;
status = "disabled";
};
soc-bus2 {
bus-id = <2>;
timer-us = <200>;
enable-msk = <0x4007>;
status = "disabled";
};
};
bus_apll: bus-apll {
compatible = "rockchip,px30-bus";
rockchip,busfreq-policy = "clkfreq";
clocks = <&cru PLL_APLL>;
clock-names = "bus";
operating-points-v2 = <&bus_apll_opp_table>;
status = "disabled";
};
bus_apll_opp_table: bus-apll-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <950000>;
};
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>;
@@ -256,28 +301,6 @@
>;
};
soc_bus: soc-bus {
compatible = "rockchip,px30-bus";
soc-bus0 {
bus-id = <0>;
timer-us = <20>;
enable-msk = <0x40f7>;
};
soc-bus1 {
bus-id = <1>;
timer-us = <200>;
enable-msk = <0x40bf>;
status = "disabled";
};
soc-bus2 {
bus-id = <2>;
timer-us = <200>;
enable-msk = <0x4007>;
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,