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ARM64: dts: rk3366: add config for display
Change-Id: I2112b26b762c56da1c621332743e376255669646 Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
This commit is contained in:
Huang Jiachai
committed by
Gerrit Code Review
Gerrit Code Review
parent
c3f8cdf6db
commit
0bb8dc17eb
@@ -43,6 +43,7 @@
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/display/rk_fb.h>
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/ {
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model = "rockchip,rk3366-fpga";
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@@ -134,6 +135,97 @@
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reg-io-width = <4>;
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};
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ion {
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compatible = "rockchip,ion";
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#address-cells = <1>;
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#size-cells = <0>;
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cma-heap {
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reg = <0x00000000 0x01000000>;
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};
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system-heap {
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};
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};
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3368-grf", "syscon";
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reg = <0x0 0xff770000 0x0 0x1000>;
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};
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fb: fb {
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compatible = "rockchip,rk-fb";
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rockchip,disp-mode = <NO_DUAL>;
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status = "disabled";
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};
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rk_screen: screen {
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compatible = "rockchip,screen";
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status = "disabled";
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#include <dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi>
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};
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lvds: lvds@ff968000 {
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compatible = "rockchip,rk3366-lvds";
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rockchip,grf = <&grf>;
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reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
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reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
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/* clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
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* clock-names = "pclk_lvds", "pclk_lvds_ctl";
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*/
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status = "disabled";
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};
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vop_lite: vop@ff8f0000 {
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compatible = "rockchip,rk3366-lcdc-lite";
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rockchip,grf = <&grf>;
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rockchip,prop = <EXTEND>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x0 0xff8f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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/* clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
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* clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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* resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
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* reset-names = "axi", "ahb", "dclk";
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*/
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status = "disabled";
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};
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vopl_mmu: vopl-mmu {
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dbgname = "vop";
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compatible = "rockchip,vopl_mmu";
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reg = <0x0 0xff8f0f00 0x0 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vopl_mmu";
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status = "disabled";
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};
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vop_big: vop@ff930000 {
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compatible = "rockchip,rk3366-lcdc-big";
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rockchip,grf = <&grf>;
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rockchip,prop = <PRMRY>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x0 0xff930000 0x0 0x23f0>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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/* clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
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* clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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* resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
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* reset-names = "axi", "ahb", "dclk";
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*/
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status = "disabled";
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};
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vopb_mmu: vopb-mmu {
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dbgname = "vop";
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compatible = "rockchip,vopb_mmu";
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reg = <0x0 0xff932400 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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status = "disabled";
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};
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gic: interrupt-controller@ffb70000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@@ -214,3 +214,66 @@
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status = "okay";
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};
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&fb {
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status = "okay";
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rockchip,disp-mode = <DUAL>;
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rockchip,uboot-logo-on = <0>;
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};
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&rk_screen {
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status = "okay";
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#include <dt-bindings/display/screen-timing/lcd-b101ew05.dtsi>
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};
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&lvds {
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pinctrl-names = "lcdc", "sleep";
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pinctrl-0 = <&lcdc_lcdc>;
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pinctrl-1 = <&lcdc_gpio>;
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status = "disabled";
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};
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&vop_lite {
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status = "okay";
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rockchip,prop = <EXTEND>;
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rockchip,mirror = <NO_MIRROR>;
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rockchip,cabc_mode = <0>;
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rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
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};
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&vopl_mmu {
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status = "okay";
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};
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&vop_big {
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status = "okay";
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rockchip,prop = <PRMRY>;
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backlight = <&backlight>;
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rockchip,mirror = <NO_MIRROR>;
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rockchip,cabc_mode = <0>;
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rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
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power_ctr: power_ctr {
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rockchip,debug = <0>;
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lcd_en: lcd-en {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* GPIO_B4 = 12 */
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rockchip,delay = <10>;
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};
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lcd_cs: lcd-cs {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; /* GPIO_D0 = 24 */
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rockchip,delay = <10>;
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};
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/* lcd_rst: lcd-rst {
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* rockchip,power_type = <GPIO>;
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* gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
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* rockchip,delay = <5>;
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* };
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*/
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};
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};
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&vopb_mmu {
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status = "okay";
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};
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@@ -45,6 +45,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/display/rk_fb.h>
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/ {
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compatible = "rockchip,rk3366";
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@@ -427,6 +428,64 @@
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reg = <0x0 0xff770000 0x0 0x1000>;
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};
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fb: fb {
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compatible = "rockchip,rk-fb";
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rockchip,disp-mode = <DUAL>;
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status = "disabled";
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};
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rk_screen: screen {
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compatible = "rockchip,screen";
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status = "disabled";
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};
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vop_lite: vop@ff8f0000 {
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compatible = "rockchip,rk3366-lcdc-lite";
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rockchip,grf = <&grf>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x0 0xff8f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
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clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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};
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vopl_mmu: vopl-mmu {
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dbgname = "vop";
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compatible = "rockchip,vopl_mmu";
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reg = <0x0 0xff8f0f00 0x0 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vopl_mmu";
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status = "disabled";
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};
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vop_big: vop@ff930000 {
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compatible = "rockchip,rk3366-lcdc-big";
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rockchip,grf = <&grf>;
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rockchip,prop = <PRMRY>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x0 0xff930000 0x0 0x23f0>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
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clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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};
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vopb_mmu: vopb-mmu {
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dbgname = "vop";
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compatible = "rockchip,vopb_mmu";
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reg = <0x0 0xff932400 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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status = "disabled";
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};
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dsihost0: mipi@ff960000 {
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compatible = "rockchip,rk3368-dsi";
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rockchip,prop = <0>;
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@@ -438,6 +497,16 @@
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status = "disabled";
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};
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lvds: lvds@ff968000 {
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compatible = "rockchip,rk3366-lvds";
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rockchip,grf = <&grf>;
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reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
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reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
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clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
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clock-names = "pclk_lvds", "pclk_lvds_ctl";
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status = "disabled";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3366-pinctrl";
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rockchip,grf = <&grf>;
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@@ -861,5 +930,51 @@
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<5 18 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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lcdc {
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lcdc_lcdc: lcdc-lcdc {
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rockchip,pins =
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<0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
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<0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
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<0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
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<0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
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<0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
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<0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
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<0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
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<0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
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<1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
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<1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
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<1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
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<1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
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<1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
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<1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
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<1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
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<1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
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<1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
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<1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
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};
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lcdc_gpio: lcdc-gpio {
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rockchip,pins =
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<0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
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<0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
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<0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
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<0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
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<0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
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<0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
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<0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
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<0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
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<1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
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<1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
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<1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
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<1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
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<1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
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<1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
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<1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
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<1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
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<1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
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<1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
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};
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};
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};
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};
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