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video/rockchip: rga2: Fix YUV output error.

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Fix some modes that did not set the U/V address and
cause the output error of the YUV format image.

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I41abd364576e0a73fd501f3dfc726eeaa6c9b118
This commit is contained in:
Yu Qiaowei
2021-03-25 16:02:38 +08:00
committed by Tao Huang
parent ae24d87219
commit 0bc139188f
1 changed files with 58 additions and 16 deletions
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74
drivers/video/rockchip/rga2/rga2_mmu_info.c
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@@ -879,7 +879,9 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
{
int SrcMemSize, DstMemSize;
unsigned long SrcStart, DstStart;
unsigned long SrcPageCount, DstPageCount;
struct page **pages = NULL;
uint32_t uv_size, v_size;
uint32_t AllSize;
uint32_t *MMU_Base = NULL, *MMU_Base_phys;
int ret, status;
@@ -895,6 +897,8 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
SrcStart = 0;
DstStart = 0;
SrcPageCount = 0;
DstPageCount = 0;
SrcMemSize = 0;
DstMemSize = 0;
@@ -908,23 +912,23 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
req->mmu_info.src0_mmu_flag = 0;
}
SrcMemSize = rga2_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);
if(SrcMemSize == 0) {
SrcPageCount = rga2_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);
if(SrcPageCount == 0) {
return -EINVAL;
}
}
if (req->mmu_info.dst_mmu_flag) {
DstMemSize = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
DstPageCount = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
req->dst.format, req->dst.vir_w, req->dst.vir_h,
&DstStart);
if(DstMemSize == 0) {
if(DstPageCount == 0) {
return -EINVAL;
}
}
SrcMemSize = (SrcMemSize + 15) & (~15);
DstMemSize = (DstMemSize + 15) & (~15);
SrcMemSize = (SrcPageCount + 15) & (~15);
DstMemSize = (DstPageCount + 15) & (~15);
AllSize = SrcMemSize + DstMemSize;
@@ -951,7 +955,7 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
&MMU_Base[0], SrcMemSize);
} else {
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
SrcStart, SrcMemSize, 0, MMU_MAP_CLEAN);
SrcStart, SrcPageCount, 0, MMU_MAP_CLEAN);
#if RGA2_DEBUGFS
if (RGA2_CHECK_MODE)
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
@@ -967,6 +971,10 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
/* change the buf address in req struct */
req->mmu_info.els_base_addr = (((unsigned long)MMU_Base_phys));
/*
*The color palette mode will not have YUV format as input,
*so UV component address is not needed
*/
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
}
@@ -976,7 +984,7 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
MMU_Base + SrcMemSize, DstMemSize);
} else {
ret = rga2_MapUserMemory(&pages[0], MMU_Base + SrcMemSize,
DstStart, DstMemSize, 1, MMU_MAP_INVALID);
DstStart, DstPageCount, 1, MMU_MAP_INVALID);
#if RGA2_DEBUGFS
if (RGA2_CHECK_MODE)
rga2_UserMemory_cheeck(&pages[0], req->dst.vir_w,
@@ -992,6 +1000,15 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
/* change the buf address in req struct */
req->mmu_info.dst_base_addr = ((unsigned long)(MMU_Base_phys + SrcMemSize));
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));
uv_size = (req->dst.uv_addr
- (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
v_size = (req->dst.v_addr
- (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) |
((uv_size) << PAGE_SHIFT);
req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) |
((v_size) << PAGE_SHIFT);
}
/* flush data to DDR */
@@ -1010,26 +1027,30 @@ static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *
{
int DstMemSize;
unsigned long DstStart;
unsigned long DstPageCount;
struct page **pages = NULL;
uint32_t uv_size, v_size;
uint32_t AllSize;
uint32_t *MMU_Base, *MMU_Base_phys;
int ret;
int status;
DstMemSize = 0;
DstPageCount = 0;
MMU_Base = NULL;
do {
if(req->mmu_info.dst_mmu_flag & 1) {
DstMemSize = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
DstPageCount = rga2_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
req->dst.format, req->dst.vir_w, req->dst.vir_h,
&DstStart);
if(DstMemSize == 0) {
if(DstPageCount == 0) {
return -EINVAL;
}
}
AllSize = (DstMemSize + 15) & (~15);
DstMemSize = (DstPageCount + 15) & (~15);
AllSize = DstMemSize;
pages = rga2_mmu_buf.pages;
@@ -1050,7 +1071,7 @@ static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *
}
else {
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
DstStart, DstMemSize,
DstStart, DstPageCount,
1, MMU_MAP_INVALID);
}
if (ret < 0) {
@@ -1062,6 +1083,15 @@ static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *
/* change the buf address in req struct */
req->mmu_info.dst_base_addr = ((unsigned long)MMU_Base_phys);
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));
uv_size = (req->dst.uv_addr
- (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
v_size = (req->dst.v_addr
- (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) |
((uv_size) << PAGE_SHIFT);
req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) |
((v_size) << PAGE_SHIFT);
}
/* flush data to DDR */
@@ -1081,12 +1111,15 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
{
int LutMemSize;
unsigned long LutStart;
unsigned long LutPageCount;
struct page **pages = NULL;
uint32_t uv_size, v_size;
uint32_t AllSize;
uint32_t *MMU_Base, *MMU_Base_phys;
int ret, status;
MMU_Base = NULL;
LutPageCount = 0;
LutMemSize = 0;
LutStart = 0;
@@ -1097,15 +1130,15 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
req->mmu_info.src1_mmu_flag = req->mmu_info.src1_mmu_flag == 1 ? 0 : req->mmu_info.src1_mmu_flag;
req->mmu_info.dst_mmu_flag = req->mmu_info.dst_mmu_flag == 1 ? 0 : req->mmu_info.dst_mmu_flag;
LutMemSize = rga2_buf_size_cal(req->pat.yrgb_addr, req->pat.uv_addr, req->pat.v_addr,
LutPageCount = rga2_buf_size_cal(req->pat.yrgb_addr, req->pat.uv_addr, req->pat.v_addr,
req->pat.format, req->pat.vir_w, req->pat.vir_h,
&LutStart);
if(LutMemSize == 0) {
if(LutPageCount == 0) {
return -EINVAL;
}
}
LutMemSize = (LutMemSize + 15) & (~15);
LutMemSize = (LutPageCount + 15) & (~15);
AllSize = LutMemSize;
if (rga2_mmu_buf_get_try(&rga2_mmu_buf, AllSize)) {
@@ -1131,7 +1164,7 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
&MMU_Base[0], LutMemSize);
} else {
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
LutStart, LutMemSize, 0, MMU_MAP_CLEAN);
LutStart, LutPageCount, 0, MMU_MAP_CLEAN);
}
if (ret < 0) {
pr_err("rga2 map palette memory failed\n");
@@ -1143,6 +1176,15 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
req->mmu_info.els_base_addr = (((unsigned long)MMU_Base_phys));
req->pat.yrgb_addr = (req->pat.yrgb_addr & (~PAGE_MASK));
uv_size = (req->pat.uv_addr
- (LutStart << PAGE_SHIFT)) >> PAGE_SHIFT;
v_size = (req->pat.v_addr
- (LutStart << PAGE_SHIFT)) >> PAGE_SHIFT;
req->pat.uv_addr = (req->pat.uv_addr & (~PAGE_MASK)) |
((uv_size) << PAGE_SHIFT);
req->pat.v_addr = (req->pat.v_addr & (~PAGE_MASK)) |
((v_size) << PAGE_SHIFT);
}
/* flush data to DDR */