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drm/rockchip: vop2: Enable dclk_div2 for YUV420 output mode

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dclk_div2 and dclk_div2_phase are undocumented in TRM, but
these two bit should be set at YUV420 output mode.

Change-Id: I711336798a7d352c8f7a85f1fedfa5933d8261ec
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2020-12-23 10:50:50 +08:00
committed by Tao Huang
parent 508d2dcbfe
commit 0bc7b9d548
3 changed files with 16 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -545,6 +545,9 @@ struct vop2_video_port_regs {
struct vop_reg mipi_dual_channel_swap;
struct vop_reg dsp_lut_en;
struct vop_reg dclk_div2;
struct vop_reg dclk_div2_phase_lock;
struct vop_reg hdr10_en;
struct vop_reg hdr_lut_update_en;
struct vop_reg hdr_lut_mode;

7
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3180,6 +3180,13 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 | vsync_len);
VOP_MODULE_SET(vop2, vp, core_dclk_div, !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) {
VOP_MODULE_SET(vop2, vp, dclk_div2, 1);
VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 1);
} else {
VOP_MODULE_SET(vop2, vp, dclk_div2, 0);
VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 0);
}
clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);

6
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -355,6 +355,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
.dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4),
.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5),
.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
@@ -428,6 +430,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
.dclk_div2 = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 4),
.dclk_div2_phase_lock = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 5),
.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
@@ -475,6 +479,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
.core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
.dclk_div2 = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 4),
.dclk_div2_phase_lock = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 5),
.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),