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synced 2026-06-09 04:10:18 +09:00
i2s : add spin_lock for i2s regiter read/write ,
fixed i2s regiter read/write obliterated when playback and captuer multithreading work status.
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@@ -33,6 +33,7 @@
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#include <mach/gpio.h>
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#include <mach/iomux.h>
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#include <mach/dma-pl330.h>
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#include <linux/spinlock.h>
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#include "rk29_pcm.h"
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#include "rk29_i2s.h"
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@@ -68,6 +69,7 @@ struct rk29_i2s_info {
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bool i2s_tx_status;//active = true;
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bool i2s_rx_status;
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spinlock_t spinlock_wr;//write read reg spin_lock
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};
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static struct rk29_dma_client rk29_dma_client_out = {
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@@ -98,6 +100,7 @@ extern int hdmi_get_hotplug(void);
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static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on)
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{
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u32 opr,xfer,clr;
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spin_lock(&i2s->spinlock_wr);
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opr = readl(&(pheadi2s->I2S_DMACR));
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xfer = readl(&(pheadi2s->I2S_XFER));
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clr = readl(&(pheadi2s->I2S_CLR));
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@@ -116,6 +119,7 @@ static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on)
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writel(xfer, &(pheadi2s->I2S_XFER));
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}
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i2s->i2s_tx_status = true;
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spin_unlock(&i2s->spinlock_wr);
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}
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else
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{
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@@ -135,15 +139,19 @@ static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on)
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writel(xfer, &(pheadi2s->I2S_XFER));
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clr |= I2S_TX_CLEAR;
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writel(clr, &(pheadi2s->I2S_CLR));
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spin_unlock(&i2s->spinlock_wr);
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udelay(1);
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I2S_DBG("rockchip_snd_txctrl: stop xfer\n");
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}
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}
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else
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spin_unlock(&i2s->spinlock_wr);
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}
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}
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static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
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{
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u32 opr,xfer,clr;
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spin_lock(&i2s->spinlock_wr);
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opr = readl(&(pheadi2s->I2S_DMACR));
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xfer = readl(&(pheadi2s->I2S_XFER));
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clr = readl(&(pheadi2s->I2S_CLR));
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@@ -162,6 +170,7 @@ static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
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writel(xfer, &(pheadi2s->I2S_XFER));
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}
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i2s->i2s_rx_status = true;
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spin_unlock(&i2s->spinlock_wr);
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#ifdef CONFIG_SND_SOC_RT5631
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//bard 7-16 s
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schedule_delayed_work(&rt5631_delay_cap,HZ/4);
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@@ -185,9 +194,12 @@ static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
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writel(xfer, &(pheadi2s->I2S_XFER));
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clr |= I2S_RX_CLEAR;
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writel(clr, &(pheadi2s->I2S_CLR));
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spin_unlock(&i2s->spinlock_wr);
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udelay(1);
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I2S_DBG("rockchip_snd_rxctrl: stop xfer\n");
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}
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else
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spin_unlock(&i2s->spinlock_wr);
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}
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}
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@@ -202,7 +214,7 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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u32 iis_ckr_value;//clock generation register
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I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
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spin_lock(&i2s->spinlock_wr);
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tx_ctl = readl(&(pheadi2s->I2S_TXCR));
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iis_ckr_value = readl(&(pheadi2s->I2S_CKR));
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@@ -243,6 +255,7 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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rx_ctl = tx_ctl & 0x00007FFF;
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writel(rx_ctl, &(pheadi2s->I2S_RXCR));
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spin_unlock(&i2s->spinlock_wr);
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return 0;
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}
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@@ -262,6 +275,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
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snd_soc_dai_set_dma_data(socdai, substream, i2s->dma_capture);
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/* Working copies of register */
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spin_lock(&i2s->spinlock_wr);
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iismod = readl(&(pheadi2s->I2S_TXCR));
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iismod &= (~((1<<5)-1));
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@@ -307,7 +321,7 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
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iismod = iismod & 0x00007FFF;
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writel(iismod, &(pheadi2s->I2S_RXCR));
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spin_unlock(&i2s->spinlock_wr);
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return 0;
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}
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@@ -372,6 +386,7 @@ static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
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i2s = to_info(cpu_dai);
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//stereo mode MCLK/SCK=4
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spin_lock(&i2s->spinlock_wr);
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reg = readl(&(pheadi2s->I2S_CKR));
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I2S_DBG("Enter:%s, %d, div_id=0x%08X, div=0x%08X\n", __FUNCTION__, __LINE__, div_id, div);
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@@ -394,7 +409,7 @@ static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
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return -EINVAL;
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}
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writel(reg, &(pheadi2s->I2S_CKR));
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spin_unlock(&i2s->spinlock_wr);
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return 0;
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}
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@@ -749,6 +764,7 @@ static int __devinit rockchip_i2s_probe(struct platform_device *pdev)
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if (ret != 0)
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goto err_i2sv2;
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spin_lock_init(&i2s->spinlock_wr);
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return 0;
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err_i2sv2:
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