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media: rockchip: isp1: fix clk gate but isp working

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power on->isp start->restart...->power off
isp reset will set clk config to default value, if
isp restart clk isn't to reconfigure.

Change-Id: I2b5ef9883c8ca5e9e142270d935f300395b0ea74
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2019-07-25 10:03:18 +08:00
committed by Tao Huang
parent a8eb21def5
commit 0cbd040137
1 changed files with 28 additions and 22 deletions
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50
drivers/media/platform/rockchip/isp1/rkisp1.c
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@@ -218,6 +218,30 @@ u32 rkisp1_mbus_pixelcode_to_v4l2(u32 pixelcode)
/**************** register operations ****************/
static void rkisp1_config_clk(struct rkisp1_device *dev, int on)
{
u32 val = !on ? 0 :
CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
writel(val, dev->base_addr + CIF_ICCL);
#if RKISP1_RK3326_USE_OLDMIPI
if (dev->isp_ver == ISP_V13) {
#else
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
#endif
val = !on ? 0 :
CIF_CLK_CTRL_MI_Y12 | CIF_CLK_CTRL_MI_SP |
CIF_CLK_CTRL_MI_RAW0 | CIF_CLK_CTRL_MI_RAW1 |
CIF_CLK_CTRL_MI_READ | CIF_CLK_CTRL_MI_RAWRD |
CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE;
writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
}
}
/*
* Image Stabilization.
* This should only be called when configuring CIF
@@ -761,6 +785,8 @@ static int rkisp1_isp_stop(struct rkisp1_device *dev)
writel(0, base + CIF_ISP_CSI0_MASK2);
writel(0, base + CIF_ISP_CSI0_MASK3);
}
rkisp1_config_clk(dev, true);
dev->isp_state = ISP_STOP;
if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
@@ -835,27 +861,6 @@ static int rkisp1_isp_start(struct rkisp1_device *dev)
return 0;
}
static void rkisp1_config_clk(struct rkisp1_device *dev)
{
u32 val = CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
writel(val, dev->base_addr + CIF_ICCL);
#if RKISP1_RK3326_USE_OLDMIPI
if (dev->isp_ver == ISP_V13) {
#else
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
#endif
val = CIF_CLK_CTRL_MI_Y12 | CIF_CLK_CTRL_MI_SP |
CIF_CLK_CTRL_MI_RAW0 | CIF_CLK_CTRL_MI_RAW1 |
CIF_CLK_CTRL_MI_READ | CIF_CLK_CTRL_MI_RAWRD |
CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE;
writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
}
}
/***************************** isp sub-devs *******************************/
static const struct ispsd_in_fmt rkisp1_isp_input_formats[] = {
@@ -1434,7 +1439,7 @@ static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
if (ret < 0)
return ret;
rkisp1_config_clk(isp_dev);
rkisp1_config_clk(isp_dev, on);
if (isp_dev->isp_ver == ISP_V12 ||
isp_dev->isp_ver == ISP_V13) {
/* disable csi_rx interrupt */
@@ -1444,6 +1449,7 @@ static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
writel(0, base + CIF_ISP_CSI0_MASK3);
}
} else {
rkisp1_config_clk(isp_dev, on);
ret = pm_runtime_put(isp_dev->dev);
if (ret < 0)
return ret;